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October 15, 2025
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Looking for external RAM and Flash compatible with STM32H743ZIT6 MCU (144 pin)?

  • October 15, 2025
  • 4 replies
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I have selected the STM32H743ZIT6 MCU for our project. Our application requires storing 22-byte data for approximately 1.5 lakh entries in RAM. Based on our calculations, we need an external memory of at least 4 MB to 8 MB. The previously considered IS61WV102416BLL-10MLI SRAM does not meet our capacity requirements. Therefore, we require a larger SRAM or PSRAM module that is fully compatible with the STM32H743ZIT6 MCU, supports memory mapping, and can interface via QSPI or asynchronous SRAM. Please provide suitable part numbers and availability details for memory options that meet these specifications.

Best answer by mƎALLEm

@sudheesh_ wrote:

Thank you @mƎALLEm .

SPI for storing data in Flash without memory mapping. Do you have any reference for this?


I think MX25L6433FM2I-08G (64-Mbit serial Flash memory) could do the job. Refer to its datasheet here.

That memory has been already used in X-NUCLEO-GFX01M2 expansion board (compatible with many NUCLEO-XXX boards).

From its schematics:

mALLEm_0-1760635331547.png

Hope I answered all your questions.

4 replies

KDJEM.1
Technical Moderator
October 16, 2025

Hello @sudheesh_ and welcome to the community;

 

From the FMC point of view, the external memory is divided into fixed-size banks of 256 Mbytes each:

KDJEM1_1-1760605991135.png

Bank 1 is used to address up to 4 NOR flash memory or PSRAM devices. This bank is split into 4 NOR/PSRAM subbanks with 4 dedicated Chip Selects.

 

For the QUADSPI interface, the memory capacity can be up to 4 Gbytes (addressed using 32 bits) in indirect mode,
but the addressable space in memory-mapped mode is limited to 256 Mbytes.

For the QUADSPI compatibility, I recommend you to verify the command format and order shared in the device datasheet must be aligned with the command format and order mentioned in the STM32 reference.

 

Thank you.

Kaouthar

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mƎALLEm
Technical Moderator
October 16, 2025

Hello @sudheesh_ ,


@sudheesh_ wrote:

Therefore, we require a larger SRAM or PSRAM module that is fully compatible with the STM32H743ZIT6 MCU, supports memory mapping, and can interface via QSPI or asynchronous SRAM. Please provide suitable part numbers and availability details for memory options that meet these specifications.


Did you make a search in the internet at least to find some part numbers?

Example:

CY62148G:

mALLEm_0-1760609269562.png

 

 

"To give better visibility on the answered topics, please click on ""Accept as Solution"" on the reply which solved your issue or answered your question."
sudheesh_Author
Associate
October 16, 2025

Thank you for your response.

I’m currently facing an issue where SRAM and SDRAM are using too many pins. Since I’m using the 144-pin package, I decided to move to QSPI. I’m using Bank 1 for flash and Bank 2 for PSRAM. This configuration supports memory-mapped read access with QSPI, so I chose this method.

Is this approach correct, or do I need to make any changes? Please provide some guidance.

mƎALLEm
Technical Moderator
October 16, 2025

Hello,

STM32H743 supports Dual-Flash mode but both device models must be identical, because in this mode the same commands and addresses are issued in parallel to both memories:

Please refer to the AN4760 " Quad-SPI interface on STM32 microcontrollers and microprocessors " Page 20.

mALLEm_0-1760619858920.png

And in your case you are planning to use two different devices Flash and SRAM!

May be you need to change the package of the MCU for a bigger one .. Or change to another product  STM32H72x/H73x that has independent OCTOSPI:

mALLEm_1-1760620289517.png

For OCTOSPI usage, please refer to the AN5050 "Getting started with Octo-SPI, Hexadeca-SPI, and XSPI interfaces on STM32 MCUs"

 

 

"To give better visibility on the answered topics, please click on ""Accept as Solution"" on the reply which solved your issue or answered your question."
sudheesh_Author
Associate
October 16, 2025

 

Thank you @mƎALLEm .
You are right, but I’m using different data lines and different chip select pins for each bank. Is this approach correct?sudheesh__2-1760623840143.png

 

sudheesh_Author
Associate
October 25, 2025

Here is my current memory section. Please review it and let me know whether it’s correct or if any modifications are required.

sudheesh__0-1761391934723.png