SPI communication issue with ADS131m08 after new isolator batch.

[SKale1]

Hello team,

We are working with the STM32F777Zi microcontroller and the ADS131M08 ADC. An isolator, the ISO7762DWR, is connected between the ADC and the microcontroller. We have configured two ADCs on a single SPI line.

Our design functions correctly with the following specifications:
ADC1-

Channels used: 4

SPI Clock: 13.65 MHz

Sampling Rate: 4000 SPS

ADC2-

Channels used: 8

SPI Clock: 13.65 MHz

Sampling Rate: 4000 SPS

However, we have recently received a new batch of the same ISO7762DWR ICs, which has impacted our system's performance. We are unable to read ADC values correctly at the above clock speed and configuration.

During troubleshooting, we found that reducing the SPI clock to below 6.5 MHz allows us to receive ADC readings. In this scenario, ADC1 (4 channels used) works fine, but ADC2 (8 channels) returns random values.

Could the lower SPI clock frequency be affecting the accuracy of the ADC readings? Also, does the number of channels used at the reduced frequency impact the ADC values?

We would appreciate your guidance in resolving this issue.

Please let us know if you require any additional information.

[Ozone]

> However, we have recently received a new batch of the same ISO7762DWR ICs, which has impacted our system's performance. We are unable to read ADC values correctly at the above clock speed and configuration.

It seems you have identified the source of the issue.

> During troubleshooting, we found that reducing the SPI clock to below 6.5 MHz allows us to receive ADC readings. In this scenario, ADC1 (4 channels used) works fine, but ADC2 (8 channels) returns random values.

This could be a power supply issue on the ADC side as well.
I would lower the SPI clock significantly (i.e. an order of magnitude), and check if these "random results" remain.
And monitor the supply voltage(s) at the ADC, especially in relation to Vref.

[Andrew Neil]

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@SKale1 wrote:

we have recently received a new batch of the same ISO7762DWR ICs, which has impacted our system's performance. We are unable to read ADC values correctly at the above clock speed and configuration..

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So, surely, that points to an issue with the isolator?

Why do you think this has anything to do with the STM32?

Have you contacted TI - it's their isolator, and their ADC:

https://www.ti.com/product/ISO7762#support-training

https://www.ti.com/product/ADS131M08#support-training

Have you got them to review the design?

 

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@SKale1 wrote:

During troubleshooting, we found that reducing the SPI clock to below 6.5 MHz allows us to receive ADC readings. 

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So look at your SPI waveforms with an oscilloscope - are they clean, and with good edges?

Look on both sides of the isolator.

 

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@SKale1 wrote:

Please let us know if you require any additional information.

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Please show your schematic.

Some good, clear photographs could help.

[Ozone]

> So look at your SPI waveforms with an oscilloscope - are they clean, and with good edges?
> Look on both sides of the isolator.

At least according to TI's datasheet, slew rates and delays are in the low nano-second range. And consequently, the datasheet promises >= 100MBit/s data rate.

Another option would be a PCB / routing issue.

But different batches of "very special" ICs exhibiting such differences in behavior and characteristics is nothing new.
I very well remember a lengthy travel to a customer of one of my former companies, complaining out test equipment "suddenly" had an excessive device failure rate. As it turned out, the producer of the ASIC the customer used for their product had "improved" his silicon, without telling them the details ...

[Andrew Neil]

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@Ozone wrote:

Another option would be a PCB / routing issue.

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Indeed.

@SKale1  The scope traces would show ...