SPI interface where slave returns a delayed clock for MISO

[Keerthi]

Hi,

 

I am using differential SPI communication with an STM32G474. The master sends the clock (SCLK) to the slave and data through the MOSI line. However, the slave responds on MOSI using a delayed clock (DCLK), which is derived from the master clock with some delay (DCLK = SCLK*Delay).

This means the master must read from the slave using DCLK instead of SCLK. I’m sure this cannot be handled through the normal SPI peripheral.

Could someone suggest a solution for this scenario?
One idea I had was:

1. Use another SPI peripheral on the STM32, configure it as a slave, and use the delayed clock (DCLK) from the slave device as the input clock to capture the return data.

Would this approach work, or is there a better method?

 

Thank you in advance

[Andrew Neil]

Please give details of the slave.

Does the device manufacturer give any suggestions on working with standard SPI Masters? It must be a common question!

 

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@Keerthi wrote:

the slave responds on MOSI using a delayed clock (DCLK), which is derived from the master clock with some delay (DCLK = SCLK*Delay).

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So does the Slave send this DCLK back to the "Master"? ie, is this an actual output signal from the "Slave"?

 

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@Keerthi wrote:

1. Use another SPI peripheral on the STM32, configure it as a slave, and use the delayed clock (DCLK) from the slave device as the input clock to capture the return data.

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Certainly sounds like something to try!

 

Or just bit-bang it?

 

[Keerthi]

Hi @Andrew Neil ,

 

Sorry that is typo. "However, the slave responds on MISO using a delayed clock (DCLK), which is derived from the master clock with some delay (DCLK = SCLK*Delay)." 

DCLK is copy of of SCLK because of the transceiver and some other components that add delay. So, sampling data with SCLK cause issue for reading data from Slave through MISO. SO DCLK is output from the slave. 

[Andrew Neil]

Again, it would help if you just provided details of the slave so we can see for ourselves!

 

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@Keerthi wrote:

because of the transceiver and some other components that add delay. 

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What transceiver?

Please post the schematic

[AScha.3]

Should work, just try it.

[Tesla DeLorean]

>>Use another SPI peripheral on the STM32, configure it as a slave, and use the delayed clock (DCLK) from the slave device as the input clock to capture the return data.

 

That was my initial thought. uSart synchronous mode might be an option, and if not too fast, one might be able to used EXTI or TIM Input Capture

[Keerthi]

Hi @Tesla DeLorean 

 

Thanks for the reply. The SPI runs at high frequencies that is 60MHz. I don't think USART works

[AScha.3]

At 60Mbit is more a job for a fpga.

[TDK]

This is not differential signaling. Sounds much more like "delayed".

Differential signalling - Wikipedia

 

Yes, a separate slave SPI instance will work to receive data.

[Andrew Neil]

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@TDK wrote:

This is not differential signaling. Sounds much more like "delayed".

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Agreed.

Title edited to better describe the situation.