STM32N65 DK - alternative for DDRAM APS256XXN-OBR-BG

[sakshi]

Hello All,

I'm working on a board, wherein i am using DRAM 256Mb 200MHz with Mfr. No: part no   APS256XXN-OBR-BG (as recommended in STM32N65 DK) but while going through it i found that this part no is not recommended for the new design. Can anyone please share the alternative of this part no or guide in this.

 

 

 

Best Regards,

Sakshi 

 

 

[KDJEM.1]

Hello @sakshi;

 

As mentioned in AN5050 section "10 Supported device", the Octo-SPI, Hexadeca-SPI, and XSPI interface can operate in two different low-level protocols: Regular-command and HyperBus.

• Thanks to the regular-command frame format flexibility, any Single-SPI, Dual-SPI, Quad-SPI, or Octo-SPI or 16-bit memory can be connected to an STM32 device. There are several suppliers of Octo-SPI or 16-bit compatible memories (such as Macronix, Adesto, Micron, AP Memory, Infineon, or Winbond).
• Thanks to the HyperBus protocol support, several HyperRAM, and HyperFlash™ memories are supported by the STM32 devices. Some memory manufacturers (such as Infineon, Winbond, or ISSI) provide HyperRAM and HyperFlash™ memories.

Also, I recommend you to verify that the command format and order shared in the memory datasheet must be aligned with the command format and order for the XSPI interface mentioned in the STM32 reference.

 

Thank you.

Kaouthar

[sakshi]

Hello @KDJEM.1 

 

Thanks for sharing the information.

Yes, I'm referring to the data sheet aswell.

 

Best Regards,

Sakshi 

[MHoll.2]

Reading the description the suggested alternative is the APS256XXN-OB9-BG.

[sakshi]

Hi @MHoll.2 

 

Thanks for the reply.

 

Best Regards,

Sakshi 

[Will_Robertson]

Hi @sakshi @MHoll.2 and @KDJEM.1 ,

Thank you very much for this discussion - it's very valuable to read your recommendations and your explaination of the Octo-SPI, Hexadeca-SPI, and XSPI interface and the Regular-command and HyperBus protocols.

Will