Designing ST25DV64K antenna

[Ide c.1]

Hi,

We want to design an antenna for the ST25DV64K NFC chip. According to the characteristics that the chip has, it needs an antenna with an inductance of 4,83 uH. Our question is if we can design an antenna with higher inductance and add a series capacitor to the chip to compensate. For example: if we create a 12.69 uH antenna, the capacitance of the chip should be 10.85 pF (ST25DV64K chip internal capacitance is 28,5 pF). Can we add a 17.52 pF series capacitor to the chip to achieve the desired capacitance? Or is it only possible to add capacitors in parallel? Thank you for the help.

Best regards,

IF

[JL. Lebon]

Hello,

Yes, it is possible to add a capacitor in series to decrease the total series capacitance seen from the antenna.

Nevertheless, you should be aware that doing this will increase the intrinsic quality factor of the tag proportionally.

Increasing the quality factor is not a bad thing, but it will increase the rise and fall time of the transmitted modulation proportionally as well.

If the quality factor is too high, the ST25DV may not be able to decode the reader command properly in low power conditions due to larger fall/rise time. It is difficult to predict the real impact as there is a lot of variables to consider.

As a consequence, you can add a serial capacitor, but a tag performance validation is necessary to ensure that it still meets your requirements in term of reading distance, in addition to tag tuning frequency validation.

Best regards.