EMVCo payment terminal design using ST25R3917B demodulation issue
Hello,
I'm designing a battery powered device with integrated payment terminal. The goal is to pass EMV Level 1 certification.
Our approach is very bare metal. We design the board, circuitry and firmware from scratch. No HAL or RFAL is being used. Our own proprietary C++ library for ST MCUs is.
For the past few weeks I've struggled with antenna matching so that Analogue Tests for Radio Frequency Power TAB111 pass on all three EMVCo Test PICCs. That's ok now and I believe my system has a proper antenna shape, impedance and Q so that the signal shape is correct.
But I'm facing issues with demodulation. In certain conditions an IRQ due to start of receive doesn't occur. Namely when Negative modulation is transmitted by PICC. Or when TEST PICC with High Linear Load is used for testing.
When no load is applied, the result of Measure Amplitude is 2.74 V, which is very close to recommended 2.8 V on RFI inputs. The voltage divider appears to be chosen correctly. Even with high load, the Voltage hovers around 1 V which is decodable if I understand it correctly.
I dived into setting up the four Receiver configuration registers. What I have noticed is that changing AM/PM demodulator to I/Q (bit demod_mode along with bit 6 amd_sel in Receiver configuration register 2) helps me with some tests, but disables other ones.
When looking for resources I found in a following video from ST, that an Application Note 4915 called EMVCo Cookbook should exist but I was unable to find it anywhere. Not sure if it never came out, or it's discontinued, but I believe it might be extremely helpful to me. Actually any detailed document about setting up a the Radio part for EMVCo purposes would be appreciated.
Thank you,
Adam
