ST25R3911B Power Sequencing

[KevinB]

In my design VDD = 2.9V and VDD_IO = 2.0V.  To minimize current when the NFC feature is not needed, I want to power down the VDD supply.  But I want to leave VDD_IO powered on.  Is there a concern with VDD being powered up and down repeatedly while VDD_IO is always on?

[Ulysses HERNIOSUS]

Hi,

IPD of the ST25R3911B is typically below 1 uA. That is what you could potentially save. 

And then removing and adding back VDD is not something we have detailed experience. VDD supplies also the VSP_D regulator for the internal logic. Removing VDD will leave this voltage floating and consuming over some longer time its buffer cap.

And likely when turning back on it can then be unclear if the internal logic (registers) has reset or not. And then you will see quite some in-rush to re-charge all the caps - voiding some of your savings due cutting VDD.

BR, Ulysses

[KevinB]

Thanks Ulysses!

In our application, VDD is powered from a dedicated buck regulator with relatively high quiescent current.  While VDD Ipd is acceptably low, we're concerned about the quiescent current of the VDD regulator.  But we can explore some other options.

While we're on this topic, are there any power sequencing requirements?  Does VDD or VDD_IO need to be turned on (or off) first?

[Ulysses HERNIOSUS]

Hi,

no specific requirements on the power-up exist. I think one could also turn off VDD_IO while not communicating but would be good to have a supply to drive IRQ pin....

Ulysses

[KevinB]

Another datasheet question.  Note 2 of Table 57 mentions a "anctl" bit which I can't find anywhere else in the datasheet.  In what register is this bit located and what is it's purpose?

Thanks!

[Ulysses HERNIOSUS]

Hi, 

anctl is a typo. You find it as antcl in the DS.

BR, Ulysses