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Visitor II
October 20, 2022
Solved

ST25R3916 FIFO read strange issue (Nucleo-L433RC-P & X-Nucleo-NFC06A1)

  • October 20, 2022
  • 1 reply
  • 1223 views

After I write to the FIFO, I read the FIFO to check if the bytes were property transferred (I understand that I cannot read and then transmit, this is just for debugging). I have a strange issue where the number of bytes in the FIFO are exactly half of what I write. Also, the bytes themselves are not what I wrote. Each time I read from the FIFO, the number of bytes in the FIFO are halved until there are zero bytes.

Here I write to the FIFO:

HAL_GPIO_WritePin(SPI_SS_GPIO_Port, SPI_SS_Pin, GPIO_PIN_RESET);

ret = HAL_SPI_Transmit(&hspi2, &FIFO_w, 1, 50);

ret = HAL_SPI_Transmit(&hspi2, &sof, 1, 50);

ret = HAL_SPI_Transmit(&hspi2, ppm_message, ppm_message_len, 50);

ret = HAL_SPI_Transmit(&hspi2, &eof, 1, 50);

HAL_GPIO_WritePin(SPI_SS_GPIO_Port, SPI_SS_Pin, GPIO_PIN_SET);

And here I read the FIFO length and FIFO itself:

HAL_GPIO_WritePin(SPI_SS_GPIO_Port, SPI_SS_Pin, GPIO_PIN_RESET);

ret = HAL_SPI_Transmit(&hspi2, &FIFO_status_addr_r, 1, 50);

ret = HAL_SPI_Receive(&hspi2, &raw_rx_len, 1, 50);

HAL_GPIO_WritePin(SPI_SS_GPIO_Port, SPI_SS_Pin, GPIO_PIN_SET);

uint8_t raw_rx[raw_rx_len];

HAL_GPIO_WritePin(SPI_SS_GPIO_Port, SPI_SS_Pin, GPIO_PIN_RESET);

ret = HAL_SPI_Transmit(&hspi2, &FIFO_r, 1, 50);

ret = HAL_SPI_Receive(&hspi2, raw_rx, raw_rx_len, 50);

HAL_GPIO_WritePin(SPI_SS_GPIO_Port, SPI_SS_Pin, GPIO_PIN_SET);

ppm_message[24] is: {0x20, 0x02, 0x02, 0x02, 0x08, 0x80...}

raw_rx[12] is: {0x10, 0x90, 0x01, 0x01, 0x01, 0x04, 0x40...}

the next FIFO read produces:

raw_rx[6] is: {0x01, 0x01, 0x01, 0x01, 0x04, 0x40}

and then:

raw_rx[3] is: {0x40, 0x40, 0x40}

and so on...

Its strange that the raw_rx looks vaguely like the ppm_message in terms of the pattern of repeated numbers.

Any help or guesses would be greatly appreciated!

Thanks,

Oliver

    This topic has been closed for replies.
    Best answer by Ulysses HERNIOSUS

    Hi Oliver,

    shifted bit patterns indicate a wrong SPI mode being used. Please check that.

    Best Regards, Ulysses

    1 reply

    Technical Moderator
    October 20, 2022

    Hi Oliver,

    shifted bit patterns indicate a wrong SPI mode being used. Please check that.

    Best Regards, Ulysses

    OSilv.1Author
    Visitor II
    October 20, 2022

    This was it. Working now with CPOL = Low and CPHA = 2 Edge.

    Thank you!