STM32H7R/S: How to configure an ADC DMA transfer in circular mode using STM32CubeMX
- November 27, 2024
- 1 reply
- 3404 views
Summary
This article provides a step-by-step guide on how to configure your STM32H7R/S to transfer ADC converted values in DMA circular mode using STM32CubeMX (version 6.12 is used).
For a complete firmware example, refer to the attached project at the end of the article.
1. Step-by-step
Step 1: Navigate to the [Board Selector] (optionally use the BSP to configure LEDs, user button and virtual com port "VCP")



Step 4: Enable the ADC channels that you need (4 channels are enabled here).
Step 5: Configuration
- Set [Continuous conversion mode] to [Enable]. This option loops the ADC. When the ADC finishes converting all its channels, it will start again from the beginning.
- Set [Enable Regular Conversions] to [Enable].
- Configure ADC 1: Set [Conversion Data Management Mode] to [DMA Circular Mode].
After the ADC converts value, it will create a request for the DMA. Circular mode here means that after the ADC finishes all the regular channels, it continues to generate DMA requests in the next run. - Set the [Number of conversion] to [4] (or your preferred value). This will set ADC to do 4 ADC
conversion which we can set.


- Select [CH0]
- Set [Circular Mode] to [Enable]
- Set [Request] to [ADC1]
- Set [Source Data Settings] data width to [Half Word]
- Set [Destination Data Settings] data width to [Half Word]
- Set [Destination Data Settings]
- Set [Destination Address Increment After Transfer] to [Enable]


Create a table of size 64 (or a multiple of 8, for example).
As the processor is a Cortex®-M7, place the table into noncacheable region (ITCM/DTCM memories (@0x0000000/@0x20000000: Not cacheable and only accessible by the Cortex® M7 and the GPDMA/HPDMA).
If the application needs to put DMA buffers in AXI SRAM (starting from @0x24000000), the user must:
- Define a noncacheable region in the MPU and linker configuration file to locate
DMA buffers (this is our choice in this example). - Ensure cache maintenance operations to ensure the cache coherence between the
CPU and the DMAs. - Disable the DCACHE (not recommended).
Find the pseudo-code below:
/* USER CODE BEGIN PD */
#define ADC_CONVERTED_DATA_BUFFER_SIZE 64
/* USER CODE END PD */
/* USER CODE BEGIN PV */
__IO uint16_t uhADCxConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE]
__attribute__((section("noncacheable_buffer")));
/* USER CODE END PV */
/* USER CODE BEGIN PFP */
static void MPU_AdjustRegionAddressSize(uint32_t Address, uint32_t Size,
MPU_Region_InitTypeDef* pInit);
static void MPU_Config(void);
/* USER CODE END PFP */
int main(void)
{
MPU_Config(void);
….
HAL_ADC_Start_DMA(&hadc1,
(uint32_t *)uhADCxConvertedData,
ADC_CONVERTED_DATA_BUFFER_SIZE
)
…
…
}
….
For a complete firmware example, refer to attached project.
2. Test results
Results in the debug windows are continuously updated as the ADC DMA transfer is in a circular mode. To check the converted values from the table, suspend the debug and analyze the result from the debug watch window.
Related links
- Reference manual 0477: STM32H7Rx/7Sx Arm®-based 32-bit MCUs
- Firmware: STM32CubeH7RS
- Knowledge article: STM32CubeIDE - How to debug STM32H7Rx/Sx project without flashing boot every time
