Accessing multiple wiznet modules using address bus decoding and single FMC SRAM nterface.

[Agour.1]

I have a requirement to interface 8 numbers of Wiznet Modules (Wiz830MJ) with STM32L496. Since i need to interface more than 4 modules so i cannot manage with standard FMC SRAM interface. So I am planning to use a decoder (74HC138D) and generate 8 different CS for modules. Please see the attachment. Remaining interface is same as standard FMC SRAM interface.

Kindly provide a feedback on this approach. If you see any issue then kindly highlight it.

[waclawek.jan]

You will have to add the decoder's delay into the total timing calculation, and you have to take into account the buses loading (which is your other thread), but that should be all.

JW