Achieve max timer clock on STM32H7

[icethi]

Hello,

I am trying to achieve the maximum timer clock on the STM32H723ZG for input capturing. In the data sheet is written under Table 4: "The maximum timer clock is up to 550 MHz depending on theTIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in RCC_D2CFGR register."

I tried to achieve this in the Clock Configuration but it seems like the only solution I found is invalid (see screenshot below). Can I still do that? Or is there another way to do that?

I tried to compile it and it worked without a problem. Sadly I cannot test it on hardware due to delivery.

Thanks in advance!

 

 

[AScha.3]

Red = wrong !

set HPRE div 2 , then get max. clk on APB1 timer clk.

try.

[icethi]

I tried, HPRE /2,  D2PRE1 /2 (137.5 MHz is max for APB1 Peripheral) and then APB1 Timer is 275 MHz. In the data sheet it is written, that 550 MHz should be possible, but I cannot find a way?

[AScha.3]

look in clock tree (i dont use H723 , so would need to download and make new project...)

there could be a separate clock mux for TIMx , like this :

of course you have to activate/enable the timer , otherwise its grey (disabled).

[STTwo-32]

Hello again @Tesla DeLorean @icethi @AScha.3 , thank you for reporting this. I will report this internally to be updated for the next release of the doc. For the Timers mentionned on the table 4 of the datasheet, the maximum frequency is 275MHz.

Best Regards.

STTwo-32