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Visitor II
August 6, 2024
Question

ADC STM32L433RCTx

  • August 6, 2024
  • 2 replies
  • 875 views

Hi,

 

While working on Nucleo Board for STM32L433RCTxx, I have configured 9 ADC channels for taking voltage inputs of 1.6 to 3.0V from individual cells of the battery.

 

I am able to get the readings but they are not consistent, a few channels are missed randomly every time I read them. I am not able to figure out what is the exact issue.

I am using DMA for getting ADC data, and length is set to half word. The .ioc file built on STM32CubeMX version 6.12 is attached for your reference.

 

Kindly suggest how I can solve this issue.

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    2 replies

    Super User
    August 6, 2024

    Why do you think some channels are missed?

    Is it perhaps an issue with your communication protocol rather than an ADC/DMA issue? Showing the evidence or code responsible for sending values would help.

    HSing.5Author
    Visitor II
    August 7, 2024

    I have configured the DMA as shown and just passing values in the variable and checking it in debug mode. Currently the values are not sent over any protocol. 

    At random some channels display some values but others don't, and this is not consistent for any channel, like if channel 1 is showing a value now then may be during the next run it might not show any value

    Super User
    August 7, 2024

    What does "some channels display some values but others don't" mean? What does a channel not being displayed look like? Screenshots would help.

    What does "not showing any value" mean?

    Again, showing code would help. The IOC file doesn't include any of your user code.

    > I have configured 9 ADC channels for taking voltage inputs of 1.6 to 3.0V from individual cells of the battery

    Are all inputs between 0 and VDDA?

    Super User
    August 7, 2024

    From the .ioc I don't know how did you set up the clocks, but if

    RCC.ADCFreq_Value=64000000

    and

    RCC.HCLKFreq_Value=16000000

    are true, and all channels' sampling time is minimum 2.5 ADC clocks, total conversion is then 14 ADC clocks which is less than 4 AHB clocks; thus the DMA simply can't keep up.

    See AN2548 for DMA timing.

    JW