DAC two channels are not working giving MCU reset behaviour

[NaveenK]

HI,

I have a custom board with STM32F405 MCU, the task is to enable PWM, set frequency, read ADC and Set DAC out voltage using CAN commands. Everything was working fine until I enabled the DAC channels, two channels were set to max DAC value(4095) and the observed the voltages as 3.02v on both the channels(Initially channel 1 was not worked, there was a ESD diode connected across channel 1 and 2, only after removing it worked). During testing different DAC values, the MCU suddenly started resetting(logs in tera term repeats) and the input power dropped to 1.5v from 12v. There was no physical short happened during testing and this type of MCU behavior won't happen just because of short. Something happened which caused damage to MCU, rest of the board circuitry is fine.

 

I request a support in understanding the issue that what could have gone wrong, Is there any special case to handle the DAC section? Since I have to move further and test the application on other board, what is the guaranty that it won't happen again so I want to analyze the issue to proceed further.

DAC section in schematic are shared below

VDDA

 

DAC output

 

 

 Kindly provide support in debugging the issue.

Regards,

 

 

[Andrew Neil]

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@NaveenK wrote:

the MCU suddenly started resetting (logs in tera term repeats)

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Have you checked the RCC clock control & status register (RCC_CSR) to find the cause of the reset?

Any clues in your logs?

[NaveenK]

@Andrew Neil 

No, Initially I thought it was a hardware failure. My hardware team has analyzed and observed that MCU is heating up, so they have replaced MCU with new one.

In logs, the very starting printf() message was flashing continuously.

[TDK]

VDDA should be tied to VDD directly or through a ferrite bead.

[NaveenK]

Here it is connected to VCC through 330R resistor and a 3v zener to ground.

[NaveenK]

@Andrew Neil @TDK 

Got it.

As per our requirement, I need to generate DAC values w.r.t 0-3v this is the reason the zener was used by taking separate net for VDD. Okay I will ask my hardware team to look into this.

Kindly conform me that if I want to use 3v VDDA then I have to use 3V LDO for VDD right?

From software side, are below points work properly please conform

1. Can both DACs be enabled at a time?

2. Can I set both DACs at max value i.e., 4095(3v)? without any load?

 

Thanks&regards

NaveenK

 

[TDK]

> Kindly conform me that if I want to use 3v VDDA then I have to use 3V LDO for VDD right?

Yes, per the datasheet.

> Can both DACs be enabled at a time?

Yes

> Can I set both DACs at max value i.e., 4095(3v)? without any load?

Yes

 

Note that the output range is not the full 0-VDDA but has some margin at top and bottom. See data sheet.

[NaveenK]

Noted.

I will repeat the test by connecting VDDA directly to VDD and will see whether the issue can be reproduced.

This time I will add a function for Checking RCC_CSR register status to know the cause of reset.