Data line not driven low enough by SD card for SDMMC.

[PhucXDoan]

I'm using a NUCLEO-L476RG with the SDMMC peripheral to interface with a microSD card. I've gotten to the point where I can read and write sectors and all, but I'm getting pretty unreliable behavior on the data bus where the SD card seems to not be able to pull the data-line low enough for SDMMC to register it. I only have 2 microSD card on hand, but both seem to exhibit this behavior.

In picture: yellow is SDMMC_CMD, blue is SDMMC_DAT0, configured to 300KHz, 1-bit wide bus.

This seems to specifically occur whenever I'm doing READ_SINGLE_BLOCK and WRITE_BLOCK back-to-back several dozen times in a row. Doing READ_SINGLE_BLOCK or WRITE_BLOCK individually in series doesn't seem to cause any problem, though this just might be a red herring. I suspect this might be a timing issue somehow, as changing the clock frequency down to 200KHz makes it much more reliable (I've yet to see the issue reproduced), and so does changing the optimization level.

I'm going to investigate the issue further, but my leading theory is that the SDMMC might be driving the data-line high while the card is attempting to drive it low, leading it to be suck above ~2.7v. Any other ideas as to what is happening here?

[mƎALLEm]

Hello, 

weird behaviour. Are you sure the pullup resistor on data line 0 is well connected?

How did you configure data 0 GPIO pin?

[PhucXDoan]

I think my hunch was correct; there seemed to be a bus contention between the SDMMC and SD card.

 

I'm using the SD card breakout board by Adafruit so it comes with the pull-up resistors and all, so that's unlikely to be the issue here.

 

I'm also confident I configured the GPIO pin correctly (AF12 for SDMMC1_D0, pin 8 on port C) since the issue I was having only occurred at very specific moments; had I set it up wrong, I probably wouldn't have been able to do continuous writes/reads for long at all.

 

What seemed to fix the issue was disabling the Data Path State Machine (DPSM) via clearing the DTEN bit in SDMMC_DCTRL after I had finish doing a transfer. This was strange, as I was expecting the DPSM to automatically disable itself after the entire transfer was complete. I'm referring to RM0351 Rev 10 January 2024.

 

My understanding is also backed up by Figure 514. Wait_R is where the DPSM would end up after receiving the 512-byte data block (coming from Receive), and it should then transition to Idle when SDMMC_DCOUNT reaches 0 and I have read everything from the RX-FIFO.

 

I'm not sure if it's a bug in my own program or something else, but I'm having it where RXFIFOE ("is RX-FIFO empty?") is not set despite the fact that FIFOCNT (remaining words in FIFO) is 0. Maybe because of the fact that RXFIFOE is never set, there is never a transition from Wait_R to Idle, thus the DPSM is never disabled?

 

If this does happen to be some sort of errata, then my current workaround of disabling the DPSM after the data transfer seems to be sufficient in removing the contention between SDMMC and the SD card.

[AScha.3]

Hi,

from DSO pic i would guess : looks like a hardware problem ->

- a lot of over/undershoot (+/- 1V !!!!)

- timing on first read maybe ok, second (write) already wrong (command and response mixed, instead of: command -- then data ) + wrong size (??) 512 byte should be same length as first 512 byte block.

- totally wrong on 3. block, command in data mixed, so looks like SDMMC driving the data-line high while the card is sending data .

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I never run sdio at so low speed - so interesting for me, that this works at all. :)

Try running it at standard speed (50MHz) and only read / mount card until this working fine, never write to card !

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Set all pins (in Cube) to medium speed + pullup on .

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Can you show a pic from your hardware you are running here ?