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Explorer II
March 31, 2025
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how to set variable latency or fixed latency for Octo-SPI PSRAM on STM32L4P5G-DK board?

  • March 31, 2025
  • 2 replies
  • 582 views

Hello,

OSPI_RegularCmdTypeDef in stm32l4xx_hal_ospi.h doesn't include ".LatencyMode" member as below.

how to set variable latency or fixed latency for Octo-SPI PSRAM on STM32L4P5G-DK board?

Thanks.

 

typedef struct

{

uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or

to the registers for the write operation (these registers are only

used for memory-mapped mode).

This parameter can be a value of @ref OSPI_OperationType */

uint32_t FlashId; /*!< It indicates which external device is selected for this command (it

applies only if Dualquad is disabled in the initialization structure).

This parameter can be a value of @ref OSPI_FlashID */

uint32_t Instruction; /*!< It contains the instruction to be sent to the device.

This parameter can be a value between 0 and 0xFFFFFFFF */

uint32_t InstructionMode; /*!< It indicates the mode of the instruction.

This parameter can be a value of @ref OSPI_InstructionMode */

uint32_t InstructionSize; /*!< It indicates the size of the instruction.

This parameter can be a value of @ref OSPI_InstructionSize */

uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase.

This parameter can be a value of @ref OSPI_InstructionDtrMode */

uint32_t Address; /*!< It contains the address to be sent to the device.

This parameter can be a value between 0 and 0xFFFFFFFF */

uint32_t AddressMode; /*!< It indicates the mode of the address.

This parameter can be a value of @ref OSPI_AddressMode */

uint32_t AddressSize; /*!< It indicates the size of the address.

This parameter can be a value of @ref OSPI_AddressSize */

uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase.

This parameter can be a value of @ref OSPI_AddressDtrMode */

uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device.

This parameter can be a value between 0 and 0xFFFFFFFF */

uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.

This parameter can be a value of @ref OSPI_AlternateBytesMode */

uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes.

This parameter can be a value of @ref OSPI_AlternateBytesSize */

uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase.

This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */

uint32_t DataMode; /*!< It indicates the mode of the data.

This parameter can be a value of @ref OSPI_DataMode */

uint32_t NbData; /*!< It indicates the number of data transferred with this command.

This field is only used for indirect mode.

This parameter can be a value between 1 and 0xFFFFFFFF */

uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase.

This parameter can be a value of @ref OSPI_DataDtrMode */

uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase.

This parameter can be a value between 0 and 31 */

uint32_t DQSMode; /*!< It enables or not the data strobe management.

This parameter can be a value of @ref OSPI_DQSMode */

uint32_t SIOOMode; /*!< It enables or not the SIOO mode.

This parameter can be a value of @ref OSPI_SIOOMode */

} OSPI_RegularCmdTypeDef;

    This topic has been closed for replies.
    Best answer by KDJEM.1

    Hello @JKim.2,

     

    Thank you for updating post.

    To clarify my last reply, the latency is not available when Octo-SPI or Quad-SPI mode is selected. Because the latency is supported with hyperBus protocol. The latency can be configured via the OCTOSPI HyperBus latency configuration register (OCTOSPI_HLCR). The reset value is 0x0000 0000.

    KDJEM1_0-1744613615241.png

     

    ->The AN5050 defines the latency mode for octal-spi PSRAM as "N/A". So, how can I know the default mode?

    In AN5050, the mode using with PSRAM APS1604M-3SQR is the Quad-SPI mode and the mode using with PSRAM APS6408L-30B-BA is Octo-SPI mode.

     

     

    KDJEM1_2-1744614129143.png

     

    You can choose the mode depending on memory datasheet.

    Thank you.

    Kaouthar

    2 replies

    Technical Moderator
    April 9, 2025

    Hello @JKim.2,

     

    The latency is supported with hyperBus protocol as mentioned in reference manual section 19.4.5 HyperBus protocol.

     

    To configure the PSRAM on STM32L4P5G-DK board, I recommend you to follow AN5050 section 7 OCTOSPI application examples.

     

    KDJEM1_0-1744190665872.png

    KDJEM1_1-1744190719354.png

     

    I hope this help you.

    Thank you.

    Kaouthar

     

    JKim.2Author
    Explorer II
    April 14, 2025

    Hello @KDJEM.1 ,

     

    The AN5050 defines the latency mode for octal-spi PSRAM as "N/A". So, how can I know the default mode?

     

    Thanks.

    KDJEM.1Answer
    Technical Moderator
    April 14, 2025

    Hello @JKim.2,

     

    Thank you for updating post.

    To clarify my last reply, the latency is not available when Octo-SPI or Quad-SPI mode is selected. Because the latency is supported with hyperBus protocol. The latency can be configured via the OCTOSPI HyperBus latency configuration register (OCTOSPI_HLCR). The reset value is 0x0000 0000.

    KDJEM1_0-1744613615241.png

     

    ->The AN5050 defines the latency mode for octal-spi PSRAM as "N/A". So, how can I know the default mode?

    In AN5050, the mode using with PSRAM APS1604M-3SQR is the Quad-SPI mode and the mode using with PSRAM APS6408L-30B-BA is Octo-SPI mode.

     

     

    KDJEM1_2-1744614129143.png

     

    You can choose the mode depending on memory datasheet.

    Thank you.

    Kaouthar