Issues with NOR Parallel Flash w/SRAM on STM32F429BIT6

[oscyzilla]

Hello,

I am trying to debug a custom board that incorporates the STM32F429BIT6. The team was noticing it was having issues with the SRAM whenever ambient temperature was increased. When I started debugging the board for the first time, I noticed a couple of other things. Touching any of the DATA line termination resistor caused issues, probing the DATA lines caused issues, and increasing the heat on the board also caused issues. 

I assumed it was a signal integrity issue and after looking at the PCB, I found a lot of issues. There are some data lines that are routed not in accordance to the AN4488 PCB Routing Guidelines. Before I recommend a respin of the board, I was looking at other alternatives that could get this to work, albeit at a slower speeds to take into account of the design issues. 

First, I want to make sure if it is possible to use the STM32F429BIT6 alongside a parallel NOR flash and SRAM. It seems that the original designer used the STM324X9I-EVAL schematic as a reference. The schematic uses a NOR Flash, SRAM, and SDRAM with the STM32F4, so I assume it is okay to use the NOR flash and SRAM part together tied to the same FMC bank as long as the #CE are different. 

The original designer also implemented 33 Ohm series resistors, similar to the eval board. Max trace length occurs on one of the ADDR lines at 2 inches. The PCB guideline states to use series resistors for traces longer than 125 mm (4 inches) to reduce reflections. Would the 33 Ohm series resistors make a significant impact on timing? We plan on testing it with 0 Ohm resistors soon. 

Lastly, are there any layout guidelines for routing the above? I am having a hard time finding guidelines, especially from STMicro. How should the ADDR and DATA lines be laid out from the uC? Should the traces go to the SRAM then to the Flash or vice versa? Can the traces go to either or as long as you pay mind to stubs, trace lenght, and crosstalk? Any input would greatly be appreciated.

 

 

[waclawek.jan]

A couple of random thoughts:

- check given pins' setting in GPIO_OSPEEDR. Not necessarily the highest setting is the optimal one

- check, if compensation cell is switched on

- ground/return arrangement (and sometimes also power supply stability/routing/decoupling) is often more critical than actual signal tracks

JW

[oscyzilla]

Hi waclawek.jan, 

Thanks for your reply. I'll ask SW to take a look at the first two. As for your last point, I did measure the power supply next to the SRAM, MCU, and NOR flash, taking into account of having a short gnd probe, and noticed minimal noise and no ripples over 10 mV. Decoupling is as per datasheet and they are placed right next to or under the BGA power pins, if applicable. 

There are some vias associated with power right next to some of these signal traces. Separation is poor, some power pins are 5 mils away from a DATA or ADDR signal. 

[FBL]

Hello @oscyzilla 

You can check PCB guidelines shared by memories manufacturers.

I think you cannot use the NOR flash and SRAM together tied to the same FMC bank address. You can check BSP example project using both memories.

 

[oscyzilla]

We don't have the NOR Flash and SRAM tied together to same FMC bank Address. 

hnor2.Init.NSBank = FMC_NORSRAM_BANK1;

hsram1.Init.NSBank = FMC_NORSRAM_BANK3;

[FBL]

Hello again @oscyzilla 

 

Simulation described in AN4803 would be helpful as well. It gives guidance on the use of external peripherals to address SI issues. 

I hope this helps.