Leakage current of STM32U585VIT3Q I/O when the Micro is not powered

[YFANG.2]

Hello

In my application, I use the DAC of the Micro to charge a capacitor(47uF). When the micro is power off, the voltage on the capacitor start to discharge with a high impedance resistor(6.8Megohm). I want the leakage current of the Micro I/O small enough. As I don't want the leakage current impact the capacitor discharge time.

Thanks!

[Peter BENSCH]

Of course, the technical data of the STM32 only apply when they are supplied with operating voltage. Every other case, including yours, must be considered separately or solved externally.

Possibilities would be, for example, anti-serially switched p-channel MOSFETs between the DAC output and the capacitor, whose interconnected gates are controlled by an n-channel MOSFET, which in turn is controlled by a dedicated GPIO. Also, a relay or reed contact would be able to disconnect the DAC from the capacitor.

Does it answer your question?

Regards

/Peter

[YFANG.2]

Hi Peter

I am not fully understand. Do you mean to add an anti-serially switched mosfet to minimize the leakage current? Do you have the relevant circuit for reference?

[Peter BENSCH]

Yes, kind of this:

 

Of course, the layout must also be low-leakage. The gates must be controlled via a MOSFET or a bipolar npn and not directly from a GPIO, because otherwise the gates cannot be switched off cleanly.

Regards

/Peter