Skip to main content
Visitor II
January 6, 2026
Question

OV5640 HREF/VSYNC polarity vs STM32H747 DCMI polarity mismatch — why does it still work?

  • January 6, 2026
  • 1 reply
  • 58 views

I'm using the STM32H747 DCMI peripheral to capture video from an OV5640 camera, and I've encountered a confusing situation regarding synchronization signal polarity.

Development Environment

  • Board: STM32H747I-DISCO

  • Camera Module: B-CAMS-OMV (OV5640)

  • Firmware: Official example project

    STM32CubeH7/Projects/STM32H747I-DISCO/Examples/DCMI/DCMI_CaptureMode/CM7/Src/main.c

OV5640 Configuration

In the OV5640 register 0x4740 (POLARITY CTRL00), I configure:

{OV5640_POLARITY_CTRL, 0x22}

According to the datasheet, this means:

  • Bit[5] = 1 → PCLK polarity: Active high

  • Bit[1] = 1 → HREF polarity: Active high

  • Bit[0] = 0 → VSYNC polarity: Active low

So the camera outputs:

  • HREF high during valid line data

  • VSYNC low during valid frame data

  • PCLK rising edge for pixel sampling

STM32 DCMI Configuration

In the STM32H747 DCMI_CR register, I configure:

DCMI->CR |= (1 << 7) | (1 << 6); // VSPOL = 1, HSPOL = 1

According to the STM32 reference manual:

  • VSPOL = 1 → VSYNC high = invalid frame

  • HSPOL = 1 → HSYNC high = invalid line

This implies:

  • VSYNC low = valid frame → matches OV5640 :white_heavy_check_mark:

  • HSYNC low = valid line → contradicts OV5640 HREF high

:question_mark: The Confusion

I connect OV5640's HREF signal to STM32's DCMI_HSYNC pin. According to the polarity settings:

  • OV5640 outputs HREF high during valid line

  • STM32 expects HSYNC low during valid line (HSPOL = 1)

This seems mismatched. Yet surprisingly:

  • Image capture works perfectly with this configuration

  • If I change HSPOL to 0 (i.e. HSYNC low = invalid), capture fails

What I Need Help With

  • Why does this polarity mismatch still result in correct image capture?

  • Are there known quirks or undocumented behaviors in DCMI signal handling?

    This topic has been closed for replies.

    1 reply

    Technical Moderator
    January 7, 2026

    Hello @fengxun2017 and welcome to the community;

     

    According the reference manual, the HSPOL and VSPOL indicate the level on the DCMI_HSYNC pin and DCMI_VSYNC pin respectively when the data are not valid on the parallel interface. 

    I didn't catch the I mismatch things. What things are mismatch?

     

    Thank you.

    Kaouthar