Problem with high speed in a custom board with STM32H735IGT6

[JVale.2]

Hi.

I am Jose Manuel. We have developed a custom board where the MCU is STM32H735IGT6, the external SRAM is APS12808L-3OBMX-BA and the external flash is W25Q128JVEIM.

The problem is that we want to work with 100 MHz, but it does not work, it just work up to 60 MHz.

We have developed a board with four levels, the same lenghts in the route and the same vias. Below, attached the interface between the SRAM and MCU. Could you please tell us what steps we have not done? Whats the recommendation to follow?

Thanks you and Best regards,

José Manuel

[Tesla DeLorean]

Even with uniform length the lines are probably still ringing / reflecting. Could can change the drive strength on the STM32 side via SPEEDR GPIO setting. Given the short length you can likely back that off significantly. Check the drive level on the W25Q side also, but likely to be low.

High speed designs would tend to have series resistors in the 27 / 33 R range to dampen the reflections and improve the matching.

The choice of command and dummy cycles can impact the burst speed as it can prefetch the page. Check also usability of DTR/DDR modes.

Caching can hide performance of the Flash NOR reading

[Tesla DeLorean]

Think of SPEEDR as a slew rate control, assuming certain loading and not just a "frequency" which ST implies. This is more about the energy being dumping into the lines, which in this case are apt to be very short, perhaps 40-50mm. You want a fast enough edge, just not all the ringing and overshoot.

ie don't use the 100 MHz settings just because that's what you think you want / need.

[BobWalance]

The 27-33ohm resistors that were mentioned by @Tesla DeLorean are very critical (assuming you have 50ohm traces). This type of termination is referred to as "source termination". They are used only for signals that have one source pin and one destination pin, and this is most common in fast-edge-rate designs.

The goal is to have the voltage level at the source (e.g., 3.3V) reach the destination pin at full voltage level (e.g., 3.3V), and also to not have any reflections reach the destination pin.

This is achieved because at the far side of the resistor, the voltage is "launched" into the transmission line at 3.3V/2.

When the waveform reaches the open-circuit at the end of the trace, the voltage is doubled from 3.3V/2 to a full 3.3V due to its full reflection back to the source. The end-reflected wave will be absorbed by the resistance of the source resistor (plus the output impedance of the driver).

This type of termination has the advantage of not having to tweak the drive strength at the source such that it is "just right". You want to make the drive as strong as possible, so you will meet your timing margins without worrying about multiple reflections. 

[JVale.2]

Hello,

Thanks for your replys.

The resistors are 33 ohms, only we have modified the resistor of the CLK to 250 ohms because it works better.

We think that the problem is in the impedance because the width of the routes is 0.2mm, so according to the impedance calculation it is 39 ohms. The possible solution is to modify the width to 0.13mm (50 ohms).

What's your opinion?

Best regards,

José Manuel

[Tesla DeLorean]

Not clear if your issue is one of signal integrity, stubs or interactions between the STM32, RAM and FLASH devices.

Check you're using the right commands and modes for the bandwidth expected.

[Tesla DeLorean]

Perhaps provide salient portions of schematics, initialization code, and data patterns showing success and failure situations? How much data reads correctly at higher speeds?

[LCE]

One more point, just to make sure: do all the signal layers have a directly neighbouring und unbroken ground plane?

Impedance is hard to control, if it is 39 Ohm in real life, try changing the resistor values. 250 Ohm in the clock line "feels" a little high. It should have the same characteristics as the other control and data lines.

And here we have the disadvantage of the big QFP package, the signals are so far apart... Maybe some crosstalk from other high speed signals? The equal-length meandering can have some drawbacks.

[JVale.2]

Hello everyone,

Data is read correctly up to 60 MHz, above 60 MHz it is not read correctly. We have spent time on the codes and we have gotten this far. We need 100 MHz to work well on a 5" sceen (with 60 MHz and a 3.5" screen, it works well).

So, we think the failure is in HW and we are going to start modifying the PCB design following the guidelines from the AN4661 document (section 8.4.3). We have answers about it:

* Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR and GND). Where do we put it? The PCB is layer 1-TOP, layer 2-GND, layer 3-PWR and layer 4-BOTTOM.

* Trace the impedance: 50Ω ± 10%. We think our actual design impedance is 36-39 ohm, can we modify the resistors in our actual PCB to increase the impedance to 50 ohms? If so, how?.

Thanks you and Best regards,

José Manuel

[AScha.3]

Hi,

i just can say, what i would do :

- leave away the funny and very professional looking meandering lines ( hey, signal speed is about 200mm/ns , so if your traces are +/- 20mm different lenght, you get +/- 100ps delays . at 10ns clock 1% error..just forget it.) so useless here.

- decoupling caps close to chip + via to power (you already have it, i think)

- in blue layer (bottom ?) almost free space, so try to do the traces short (avoid this big loop areas, you have now on some (this pick up fields and emit emv... :) ), try to bring them close together to form a bundle between cpu and ram. (but not too close, to avoid to much capacitive coupling ! about 1mm distance, if possible)

- the damping resistors could be 33...150r , i would start with 75 ohm , in all traces same value.

- position of this resistors is not important (you anyway never get a "correct" transmission line, this would need termination impedance on both (!) ends - forget this here); position need not to be close to chip/pin; just (without resistors )try to find direct , short and bundled traces from cpu to ram and then insert the damping resistors, where you have room and not generate useless loops and deteriorating bypass loops.

+ show your design, if you want some checking , before production ...

[LCE]

You should increase the PCB track impedance slightly up to 50R. If your PCB software cannot calculate the width for you, there are many calculators online.

Resistor placement: they should be close to the source, which is not to determine for the data IOs, but you should put at least the resistors for CLK, DQS, NCS close to the MCU. Just as I write this , I see that on the H735 Discovery Board they put all the resistors close to the HyperRAM, and that is working here with 100 MHz.
So I don't know...

[Piranha]

Generally the most important factor is not to make a 50R impedance, but to match the same impedance from the source to the destination and in between. The lesser the points, where the impedance is changing, the better. The series resistors have to be added at the source (output) so that the output driver's and resistor's impedance added together matches the chosen target impedance. On bidirectional pins generally one must put the series resistors on both ends and match them with the respective output drivers. Some chips for some interfaces can have an output drivers, which are already matched for some specific impedance and therefore doesn't need an additional resistors for that particular impedance. Also on some denser and/or cheaper boards ST omits the resistors on the MCU end because STM32 microcontrollers have a drive strength configuration for outputs and that partially solves the impedance matching issues.

As ST mostly uses 33R resistors and targets for 50R impedance, one can assume the output driver's impedance as 17R. Therefore, if your current actual PCB design impedance is closer to 39R, then just use 22R resistors for this design.

But take a note that, for example, USB and Ethernet interfaces require 90R and 100R differential impedances. That is a requirement for the external signals of the PHYs, connectors and wires, not the internal CMOS level and other signals, of course. Therefore for such interfaces one cannot choose any impedance, but has to adhere to the standard.

And, if it's impossible to match the impedance properly, it becomes even more important to make those wrong routes as short as possible.

[Sco]

Hello 

From hardware point of view:

1. the equal length of the signals are very important = > resistance matching(here should be 50ohm).

2. another important point is that you need to make sure the reference GND, in your picture, can't see the GND layer directly, are layer 2, layer 3 with good GND here(as a reference for the signals).

3. when you talk about the resistor on board, the resistors should be near the source side(MCU).

[JVale.2]

Hello,

1. The length of the signals are equal, approximately 51 mm. Our possible failure is the impedance, so we will modify the widht of the signals.

2. Layer 1 is TOP (red), layer 2 is GND, layer 3 is PWR (3.3V), layer 4 is BOTTOM (blue). According to the AN4661 document (section 8.4.3), we should put 10nF capacitor, but... how? where?

3. On the evaluation kit (STM32H735IG-DK), the resistors are close to the SRAM.  So is it a other possible failure? Can we solve it moving the resistor to the outside of the MCU?

Thanks you.

[Sco]

1. Regarding the resistance matching, it depends on the width of the signals, the stack, the process of PCB manufacturing company. I can't judges if the width is ok or not, I suggest you to communicate with PCB manufacturing company: make it clear that you request them to do the resistance matching with 50ohm(refer to L2/L3), they will adapt the width and back to you with an EQ file. You can communicate until you get what you want.

2. Always for each power, there should be a/several bypass caps(to GND) with value 100nf, 1uf... as described in the document(AN4661 section 8.4.3), it recommends 10nF, it means the Power which these signals(memory) refer to, for such power, there should be a 10nF cap to GND.

3. For this point, it's better to place these resistors close to the MCUs, but I can't judge it's this point that casues the failure. I recommend you to check the shcematic and layout carefully besides this point.

[LCE]

2. 10nF capacitor:

Best would be to put a few of these at source and destination, and close to the vias where the high speed signals change layer. Think of the caps as the helping the signal GND return path via the VCC plane.

I prefer GND planes only, if not enough layers are available maybe I would use a GND plane for some power supply lines, but only if these would not cross any critical signals on the next layer.

But even with GND planes only, put a few stitching vias (GND to GND) close to the vias where the signals change layers.