QSPI external loader issue

[Buelent Cakir]

Posted on November 02, 2017 at 10:29

Hi,

I'm using a S25F064F Flash on a custom STM32F446RC Board. Due the 64Pin Version of this Controller the Flash are connected as QSPI-DUAL (means only two data lines).

My issue with the attached Code is, that I can Programm only one Page even I get the error

10:06:41 : The elf loader Program function fails.

10:06:41 : Memory-Loader error

10:06:41 : Error occured during program operation!

10:06:41 : Programming error @ 0x90000003!

Afterward I see only one Page (256Bytes) programmed.

Similiar issue with the erasing of sectors. Only the first Sector are erased.

I can't see what is Happening in the Background and what is the ST-Link Util doing.

Maybe someone could have look in the Code and could found an issue.

Many Thanks in advance.

#qspi-flash #st-link-external-loader

[Buelent Cakir]

Posted on November 02, 2017 at 14:53

I'm wondering why ST either don't give a good documentation or more examples based on HAL Drivers.

Within the application the QSPI programming and reading is working fine, but not in the external loader, because of no documentation.

[Tesla DeLorean]

Posted on November 02, 2017 at 16:41

Well the engineers used the SPL to build them originally, and I think there is also some expectation that those doing this kind of board bring-up and design have done these types of loaders before. SoC designs come with nothing. The loaders are similar to those from Keil or Segger. Work with the ST FAE supporting your account.

Would suggest building a test framework to run the plug-in, and instrument using the USART to output debugging/telemetry.

Error suggests verify readback is failing, either the data isn't matching or routine returning a code suggesting it doesn't. Kind of situation where you need hardware to evaluate dynamically.

Sorry, not downloading a dozen plus files, consider ZIPing up and presenting as a buildable project. Not sure the number of people here using IAR, F4 and 

S25F064F

[Buelent Cakir]

Posted on November 05, 2017 at 19:01

Hi Clive,

I fully agree to you, but I would expect from ST a propper documentation for the external loaders.

To have more visibility what is Happening during the calls I implemented UART Communication for some debug Outputs, but this is making the Situation worst.

With this uart transmit the external loader doesn't work at all, it stopping.

For example the Read funvtion works well without UART Transmit, but with it's not working. Withion the init Phase I'm tranmsiting the 'start' string and this showing in the Receiver, means the uart itself is working.

[Buelent Cakir]

Posted on November 05, 2017 at 19:04

Now I add the whole IAR Project Folder

[AVI-crak]

Posted on November 05, 2017 at 20:16

I could not find the documentation for the S25F064A memory, but there is documentation for the S25FL064A.

A very flawed memory chip, without the support of QSPI mode.

[Buelent Cakir]

Posted on November 05, 2017 at 20:31

Hi,

this is the Datasheet

http://www.farnell.com/datasheets/2309630.pdf?_ga=2.1435061.546026651.1509910079-83521258.1470258912

Why do you think that this Flash would be flawed?

[AVI-crak]

Posted on November 05, 2017 at 20:57

S25FL064A

Memory with the letter 'A' - can only work in spi mode. The older the letter - the more opportunities.

For the letter 'P', QSPI mode is available.

For the letter 'L', DDR mode is available.

But you have the letter 'F' - it's just a higher frequency and an additional protection system.

[AVI-crak]

Posted on November 05, 2017 at 22:18

The last letter in the name of the flash memory is the revision of the chip. The letter defines the possibilities.

Find the documentation for your chip with the full match of the name, the last letter is very important.

[Buelent Cakir]

Posted on November 06, 2017 at 11:06

Ok, the last Letter is 'L'. That means, that the Flash has QSPI capabilities.

Thanks

[AVI-crak]

Posted on November 06, 2017 at 18:58

The S25FL064L chip has a fascinating user identification algorithm (page 53). This algorithm begins with the power supply, or software restart. Protection is designed to store content in secret, and has three levels:

1) no password no protection.

2) there is a password, there is protection for all space or separate sectors without write protection.

3) there is a password, the protection is removed by reading the first correct address (not zero).

This algorithm must be passed in spi mode, after register access registers are available (their main number is 25). I have to admit - this chip can save the business, the program code will remain a secret.

Then routine actions are performed.

Adjust the power regulator.

Configuring data bus latencies.

Setting the command word mode (do not touch).

Setting the data bus mode.

Switch mode to flash.

Switching the spi mode to QSPI on st.

Test read / write.

A cursory examination of LOADER_SRC_H program code - gives some mismatches of command words with documentation.