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Visitor II
December 15, 2022
Solved

Request review schematics & PCB using STM32F401VET6(expecially ESD)

  • December 15, 2022
  • 3 replies
  • 2763 views

Dear STMicroelectronics,

The attached file is a product circuit diagram applying STM32F401VET6 as the main CPU.

As for the inquiry, there is a problem that the CPU standard output HIGH signal drops to LOW signal at a specific PORT when performing ESD test.

The specific PORT is as follows.

 =>PB2,PB3,PB4,PB5,PB6,PB7,PB8,PB9,PB10,PB12,PB13,PB14,PB15,PC0,PC1,PC2,PC3,PC4,PC5,PC6,PC8,PC9,PC10,PC11. PC12, PC13

 => A specific PORT is the input signal (Base) of the PNP Transitor-applied switching circuit, and functions to turn on (High) and turn off (Low) the LED.

Please review the attached circuit diagram and PCB.

Thank you.

    This topic has been closed for replies.
    Best answer by Jaroslav JANOS

    Hi again,

    first of all, the ESD level of STM32F401xE alone for IEC 61000-4-2 is 2B according to datasheet, which is under 1kV (see AN1709).

    To improve this:

    1. Consider switching from 2 layer to at least 4 layer PCB, to improve return paths in GND.
    2. The protection resistors can limit only the current. Consider placing some other protection devices, ideally TVS diodes. Refer to AN5612 for selecting best ESD protection components for your application.
    3. It would be better, if the tracks to the connectors were much shorter.
    4. Remove R181, there is already an internal pull-up on NRST pin.

    BR,

    Jaroslav

    3 replies

    ST Employee
    December 15, 2022

    Hi @Inho Jeon​,

    could you please clarify what kind of ESD test is failing? Is it IEC 61000-4-2, or other? Also at which ESD level does this behavior occur?

    BR,

    Jaroslav

    Inho JeonAuthor
    Visitor II
    December 16, 2022

    Dear ​Jaroslav,

    Yes, It is failed at contact -4KV of ESD on IEC 61000-4-2.

    Thank you.

    Best Regards,

    Inho Jeon

    Graduate II
    December 16, 2022

    Where's the contact happening?

    I haven't seen any protection diodes / varistors / whatever, so you purely rely on the ICs' ESD capabilities?

    Problem with that: you cannot control the (over-) current flow.

    Think like: where's the current flowing? Probably within / through the device then through system GND. And then you're probably f*****. ;)

    That's why external protection "devices" make sense, and best practice to connect their GND not "somewhere" to PCB GND, ideally to some other low impedance path, e.g. metal case.

    ST Employee
    December 16, 2022

    Hi again,

    first of all, the ESD level of STM32F401xE alone for IEC 61000-4-2 is 2B according to datasheet, which is under 1kV (see AN1709).

    To improve this:

    1. Consider switching from 2 layer to at least 4 layer PCB, to improve return paths in GND.
    2. The protection resistors can limit only the current. Consider placing some other protection devices, ideally TVS diodes. Refer to AN5612 for selecting best ESD protection components for your application.
    3. It would be better, if the tracks to the connectors were much shorter.
    4. Remove R181, there is already an internal pull-up on NRST pin.

    BR,

    Jaroslav