Seeing opposite behavior expected from an open drain output?

[BSunw.1]

I am working with the NUCLEO-L552ZE-Q and have made a very simple test circuit to test an open drain output signal. I have the pin configured as an open drain output with no pull up or pull down with the signal pulled up to 3.3V through a 1K resistor. When I SET the pin, I see a 3.3V signal probing on the bottom side of the 1K resistor and when I CLEAR the pin, I see a 0V signal. This is opposite of what I would expect? Is there some inverting buffer that is connected to the gate of the fet?

[Peter BENSCH]

How did you set/clear the GPIO?

It would be best if you included an excerpt from the program so that one can understand what you did.

Regards

/Peter

[KnarfB]

This is expected behaviour. If you set push-pull output mode, this is clearly the way it should be. When you set open-drain, the only difference is that the upper PMOS fet is left open (high impedance) all the time.

See also AN4899 Application note "STM32 GPIO configuration for hardware settings and low-power consumption"

hth

KnarfB

[BSunw.1]

I used the HAL and CubeMx GUI to generate the GPIO initialization for me. Here are some screen shots.

GPIO Config:

 

Simple code:

 

Here is what my test circuit looks like:

 

All I am doing is starting a debug session and executing the RESET and SET GPIO commands one at a time to read the output on an oscilloscope. As I said, when I RESET the pin, I see a voltage of 0V on the probe and when I SET the pin, I see a voltage of 3.3V on the probe. This is backward of what I expect if I am driving the NMOS fet as shown from AN4899:

[TDK]

> This is backward of what I expect if I am driving the NMOS fet as shown from AN4899:

But that's not what SET and RESET mean in the context of the code. SET is logic high, RESET is logic low.

In OD and PP, if you want logic low (i.e. you want to drive the N-MOSFET), the pin needs to be RESET, as KnarfB stated above.