ST-LINK/V2 SWD Incorrect Connection Protection

[adamrosy]

Hi there,

I'm designing a very compact PCB. For the debug header I'm using 4-wire SWD with a 2x2 header on the board (specifically CLP-102-02-L-D). There's no keying or polarisation meaning that the programming lead could be plugged in in four different orientations, potentially connecting MCU VDD/GND from the ST-LINK to any of the pins on the board. Hopefully this image illustrates the (potential) problem:

I haven't been able to find if there is any concern with connecting incorrect pins together. I know MCU VDD is a measured voltage, my only concern would be connecting GND from the ST-LINK to +3V£ on the board side; could this cause a short or is this all protected on the ST-LINK side? I have struggled to find a header that is small enough with some kind of keying to prevent invalid connections, but if there is a real possibility of damage to the board I will need to rethink this!

Thank you for your help.

[jiangfan]

You want 2x2 header with 1.27mm pitch. keying and polarity are preferred.

something like TFM-102-01-L-D-WT may be considered.

TFM-102-01-L-D-WT - High-Reliability Tiger Eye™ Terminal Strips, .050" Pitch | Samtec

[jiangfan]

from signal point of view, +3V3 is not mandatory. If I remember correctly, +3V3 on board side is to provide target Vdd voltage only, and user may connect on board 3.3V (target Vdd) via resistor (1k may be OK) to +3V3 pin of 2x2 header. then a short will not happen mostly.

[adamrosy]

Hi @jiangfan 

Thank you for the header suggestion. While that header would definitely be preferred, I'm very limited space wise, and only have maybe a maximum 4x4 mm area to put a header, which is why I'm using the smaller CLP variant. I couldn't find anything at that size with polarization.

Adding a protection resistor sounds like a good idea, I will test out if this works without issue and then I will look to fit one in.