st-link v3 error when debug cortex m7 code in ram and I-CACHE enabled.

[Poul-Erik]

I am moving a smt32H750 application from flash to ram. In flash the st-link v3 works fine both single step and break points, but when moved to ram, it is diffucult to get the ST-LINK breaking the program. If the main-loop is extended (cache not cover all code) the break-point work. If I disable the I-cache it works). If I replace the ST-LINK by a J-LINK from Segger, it works.

Bert regards PEH.

[Tesla DeLorean]

I could see that being a pain. Perhaps the other tools just turn off caching, doing a cache-clean is likely more disruptive.

Does it work better if you use ITCMRAM?

[kgardas]

I'm hit by the same issue. I've reported it here: https://community.st.com/s/feed/0D53W00002BBBlsSAH -- and most importantly based on forum user advice I've also reported it to the ST.com support. They assigned some engineer to it so there is perhaps a chance someone will officially tell what to do about it.

[kgardas]

And here is the support case: https://community.st.com/s/case/5003W00000OgwxTQAR/stlink-gdb-server-breakpoints-placed-into-sramsdram-are-not-working-well