STM32F769I-EVAL SDRAM information

[ANauz.1]

Hello,

I'm working on the STM32F769I-EVAL.

In the User Manual 2035, version 3 (last version), on the SDRAM schematic, the address pin are mapped such as:

• A0 to A11 are connected
• A12 and A13 are not connected
• A14 and A15 are connected

So I have some question about it:

• What is the purpose to connect A14 and A15 when A12 and A13 are not connected. The maximum bus address width will be A0-A11, and other could not be used
• With a 12bits address bus, the maximum addressable 32bits is 4096. With the four bank, it make 16384. The documentation, §6.13 indicates 8M*32bit. How to access all the 8M? (should be 21 address bit, to have 2M in each of the 4 banks)

Is this a limitation of the board, or is there an error on the schematics? Or maybe there is something I do not understand.

Can someone explain me a little more? Thank you

Antoine

[ANauz.1]

Ok so... I completely miss the fact that the SDRAM is working with 13-bits Address Row AND 11-bits Address Column

It makes 8192 * 2048 = 16 777 216 so 16M 32Bits, or 64MBytes for each bank, and a total of 256MB.

The A14 and A15 are mapped on the BA0 and BA1, Bank Address.

Now every thing is clear!

[Harvey White]

As a side note, the F469I disco board does the same kind of thing, mapping higher address bits to the bank select bits.

Try making a dummy project with the board, select "initialize all peripherals to default" and then check the connections in the .IOC file.

they should be correct for your board, another way of verifying the design.

[ANauz.1]

I just made a test with a default configuration, and... strange but the FMC configuration for the SDRAM is set to 13bits for address, while Shematics AND SDRAM datasheet show a A0-A11 so 12bits address bus!

I was wrong in my previous post. The SDRAM is:

• 12bits row address (2^12 = 4096)
• 9 bits column address (2^9 = 512)
• 4 bank

For a total of 4096 * 512 * 4 = 8388608 or 8M as specified in the datasheet.

In the default IOC, address row is 13bits and column is 8bits. It is the same addressable number of address, but address row should be 12 and column 9.