STM32H7 DSI – Support for 640×480 Display vs DSI Bandwidth Limits

[Shivani]

Hello everyone,

I am working with an STM32H7 device using the DSI host interface and would like some clarification regarding supported display resolutions.

As per the STM32H7 datasheet, it is mentioned that:

“Extended resolutions beyond the DPI standard maximum resolution of 800×480 pixels; the maximum resolution is limited by the available DSI physical link bandwidth.”

Based on this statement, I would like to confirm the following:

• Can a 640×480 display be reliably connected to the STM32H7 using the DSI interface?

• Are there any practical limitations related to DSI lane count, lane speed, or refresh rate that would prevent using 640×480, even though it is below 800×480?

• Has anyone successfully driven a 640×480 display (at 60 Hz or other refresh rates) on STM32H7 using DSI + LTDC?

• Is the limitation purely bandwidth-based, or are there additional constraints in the STM32 DSI/LTDC implementation?

Attaching the clock configuration of STM32CubeMX of DSI.

Any insights, calculations, or real-world experience would be greatly appreciated.

Thank you in advance.

Best regards,
Shivani

[MM..1]

Why you mean this resolution is problem ?

Only one bottleneck exist RAM for framebuffers and count of buffers. PCB design right routing for DSI and external memories.