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February 20, 2025
Solved

STM32H747 Disco board and USB HS at 1.8V VDD

  • February 20, 2025
  • 2 replies
  • 2071 views

Hi,
I´m trying to get a STM32H747 Discovery board together with USB Host to operate at 1.8V VDD.
At 3.3V VDD_MCU USB is working fine!


What I´ve done:
1. Removed jumper on JP3 and supplied VDD_MCU with 1.8V.
2. Removed SB10 and supplied VDD33USB with 3.3V.
3. Removed R33 and supplied USB_VDDIO (pin 32 on USB3320) with 1.8V.
4. Verified that R136 is not mounted and R137 is mounted.

What is working:
A. The MCU is working fine at 1.8V. I´m running at 400MHz at voltage scale 1 (using the SMPS).
B. VBUS is started (USB3320 controls U2) and LD7 lights up.
C. When a usb device is inserted, its looks like its recognized. The usb stack connects a device, initiates a reset and then I get Control Errors. 

A had a look around the forum and found this post:
https://community.st.com/t5/stm32-mcus/how-to-check-compatibility-on-usb-ulpi-transceivers-with-stm32/ta-p/657275
However, the REFCLK for the USB3320 is 24MHz, so not sure that post above is what I´m seeing.

The reason I need 1.8V IO operation is that I´m using a Wifi module (connected via SDIO interface) that only support 1.8V IO.

My best guesses/questions:
1. Some timing is violated.
2. X1 is supplied with 3.3V so REFCLK for is at 3.3V IO. But according to datasheet (USB3320), Voh for REFCLK is between 0.68 *VDD18 and VDD33 (internally generated by USB3320). So this should not be an issue.
3. It is not clear what IO level the ULPI interface of the STM32H7 is referenced to when assigning a pin to an alternate function (OTG_HS_ULPI_X). VDD or VDD33USB. 
4. Something that I completely missed...

    This topic has been closed for replies.
    Best answer by FBL

    Hi @AJans.3 

    For High-speed operations, STM32H747 need a PHY that can operate at 60 MHz. ULPI specification provides specific requirements for the timing of all control and data signals that are used in the ULPI interface.

    • ts(IN)  ≤ (Clock period (tCLK) – tv(OUT)max
    • Clock period (tCLK) =1/60MHz=16.66ns
    • tv(OUT)=tDC/tDD Data/control output delay depends on supply voltage (14ns in your case as you mentioned)
    • clock setup/hold time = 6ns (according to PHY transceiver)

    FBL_1-1740145597045.png

    This means, at 1.8V, you should look for a different ULPI PHY to meet the requirements. 

    This requirement is mandatory to allow a USB peripheral to wake up in time to respond to chirp signaling.

    2 replies

    Super User
    February 20, 2025

    Hi,

    i didnt check in ds now - but :

    > supplied USB_VDDIO (pin 32 on USB3320) with 1.8V

    If this is for the USB IO signal, it needs 3v3 ; USB has 3v3 signal levels.

    AJans.3Author
    Explorer
    February 20, 2025

    Hi, 

    Thanks for the reply.
    No this is the IO voltage supply level for interfacing with host (STM32H7).
    USB3320 is supply with 5V and then it internally generates a 3.3V that is used for the actual USB (DP/DM) signaling (at least my interpretation).

    I´ve just done a deep dive in the datasheet and found that 
    PB12 - ULPI_D5
    PB13 - ULPI_D6

    is a _u I/O structure and is supplied by VDD33USB. So right now I have 2 signals in the ULPI interface at 3.3V IO and the rest at 1.8V. 

    But its still unclear if VDD33USB must be 3.3V for the USB block to work properly or if it can be 1.8V when not using the internal FS phy (which I´m not). 

    Super User
    February 20, 2025

    So just set it on 3v3 and see: working better - or not.

    Technical Moderator
    February 20, 2025

    Hi @AJans.3 

    You need to make sure ts(IN) = 5 ns ≤ (Clock period (tCLK) – tv(OUT)max)

    Check this article for more details

    How to check compatibility on USB ULPI transceiver... - STMicroelectronics Community

    AJans.3Author
    Explorer
    February 20, 2025

    Hi @FBL ,

    is this really a problem in my case?

    The disco board use a 24MHz clock and from what i can read from that post:

    5ns < 1/24MHz - 14ns (from stm32h747 datasheet at 1.8V)

    So 42ns - 14 =28 ns.

    Im probably not understanding this…:grinning_face:

    FBLAnswer
    Technical Moderator
    February 21, 2025

    Hi @AJans.3 

    For High-speed operations, STM32H747 need a PHY that can operate at 60 MHz. ULPI specification provides specific requirements for the timing of all control and data signals that are used in the ULPI interface.

    • ts(IN)  ≤ (Clock period (tCLK) – tv(OUT)max
    • Clock period (tCLK) =1/60MHz=16.66ns
    • tv(OUT)=tDC/tDD Data/control output delay depends on supply voltage (14ns in your case as you mentioned)
    • clock setup/hold time = 6ns (according to PHY transceiver)

    FBL_1-1740145597045.png

    This means, at 1.8V, you should look for a different ULPI PHY to meet the requirements. 

    This requirement is mandatory to allow a USB peripheral to wake up in time to respond to chirp signaling.