stm32H747 disco Data Sharing

[Hiram Hyman]

Hi, 

I'm running into issues writing to SRAM4 buffer (0x38001000). Apparently, there isn't any empty locations for  (0x38001000-(0x3800FFFF)) address. 

I currently have the M7 to service as a user interface (basically 3 screens) to access the M4 peripherals for motor control. In short, the goals is to receive an integer (10-100) to set the instance of the PWM. 

The issue that I'm having is not being able to write to SRAM4 for the locations that I provided. An empty location  throughs a  fault error. I thought this area is pretty much a reserved as user needed location. Additionally, there's data that's being wrote to it from someplace. 

Does this have anything to do with the linker or the screen Data? I'm learning so, I don't know. Can you please help?

Thanks in advance,

[TDK]

The memory addresses used will be shown in the linker file. If data is being written there, it's probably defined as a usable region.

Keep in mind you have a dual core chip, so either the M4 or the M7 could be using that space. Your linker files should provide the answer.

[Hiram Hyman]

Hi, 

Thanks for your reply. In terms of the CM7, I came across this code:

/* Highest address of the user mode stack */

_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1); /* end of "RAM_D1" Ram type memory */

 

_Min_Heap_Size = 0x1000 ; /* required amount of heap */

_Min_Stack_Size = 0x1000 ; /* required amount of stack */

 

/* Memories definition */

MEMORY

{

RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K

FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* Memory is divided. Actual start is 0x8000000 and actual length is 2048K */

DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K

RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K

RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K

ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K

}

 

I've seen examples where the D3 address was provided in the linker but, I need to learn more about

the modifying of the linker code before attempting to do so.

 

 While providing

#define sram4 0x38000000

I can provide values to 0x38000000 from CM7-CM4 and with a little more work, do the same for CM4-CM7 using

memcpy(). All of the data that I expected is present via this way.

However, using

#define shared_data ((shared_data_TypeDef *) 0x38000000) doesn't work and this is when I receive

data from some place else it seems.

 

Can you let me know if I'm on the correct course to be able to share data between cores on the

STM32H747-Disco? Also, I have enabled CM7 Shareability.

 

Thanks for you assistance!

Hiram Hyman

[TDK]

> Can you let me know if I'm on the correct course to be able to share data between cores on the STM32H747-Disco?

Yes, what you describe can work. Both cores can access that portion of memory. You need to be aware of cache on the M7, or mark the region as non-cacheable or something, but the scheme should work.

> RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K

You have RAM_D3 defined in your linker script, which includes the SRAM4 addresses. Remove that from the linker so the memory isn't used by the linker.

Be aware there is a linker file for the M4 core and for the M7 core. You need to ensure that neither of them uses the addresses you want to utilize.

[FBL]

Hello @Hiram Hyman,

Here is an example to learn about manipulating the linker script.

How to Create a Super Simple Bootloader, Part 1: Getting Started - YouTube

Also, this link will help you to synchronize between the cores to access SRAM4. MaJerle/stm32h7-dual-core-inter-cpu-async-communication: Inter-CPU asynchronous communication between Cortex-M7 and Cortex-M4 cores on STM32H7 dual core devices (github.com)

Hope this helps!

[Tesla DeLorean]

Make sure the appropriate RAM clocks are enabled. ie RCC_AHB2ENR_D2SRAM3EN etc

The cores may have the memory at different addresses. Each linker should be given it's own sandbox to allocate. For stuff that you have in common, suggest using a structure both applications share, and use a pointer to that structure. Determine who initializes it, determine who gets to write or read what, and how ownership to modify is owned/arbitrated. Watch for write buffers and cache coherency.