STM32L4P5 FT pins tolerant up to 5V even if supplied power to STM is 1.8V?
I have STM32L4P5CGU6 (48 pin).
Pins PB5, PB4, PB3, PA15 are used as SPI1 with another IC which has 3.3V levels.
As well as PB6, PB8, PB9 as custom input GPIOs with voltage levels of 3.3V.
VDD (pin #9, pin#24, #48) -> 1.8V
They all seem to work fine, however, I was wondering about long-term effects on such FT gpios, and to get a clarification on VDD_FT and how it works.
Reference manual RM0432 p. 334, fig. 26 shows 5V tolerant pins, there's a protection diode to VDD_FT.
AN4899, on p.9 says: "The voltage level called VDD_FT in some datasheets and reference manuals is inside the ESD protection block"
On p.17:
"STM32 devices embed five-volt tolerant GPIOs. These GPIOs are actually tolerant to
VDD + 3.6 V. It means that the I/O pins can accept such voltages without causing leakage
current and damages on the GPIOs."
Regardless of the supply voltage, VIN cannot exceed 5.5 V."
So FT Pins have no direct connection to STM's VDD, correct? But there's a protection diode from such a pin to VDD_FT? Where does VDD_FT connect to? How does schematic associated with it looks like?
