Support for Parallel Read and Write Operations on Octal SPI Flash in FreeRTOS

[sohm]

We are looking to work with the STM32U5A9J-DK Discovery kit, which features the STM32U5A9NJH6Q MCU. Our application requires the use of the Octal SPI flash memory in a FreeRTOS environment. Specifically, we need to perform simultaneous read and write operations on the flash memory from two different threads.

1. Does the Octal SPI driver support parallel read and write operations.
2. Can we perform simultaneous read and write operations from different threads?
3. Are there any limitations or specific considerations we should be aware of when attempting to implement this functionality?

Thank in advance.

 

 

[KDJEM.1]

Hello @sohm and welcome to the Community :),

To support the read while write mode:

• Needs memory supports the RWW mode like as MX66UW1G45G.....For MX66UW1G45G supports the RWW, so if any Program or erase is done in one bank, another bank can be read at the same time. 
• Needs 2 hosts controllers (OCTOSPI)+ IO manager
• One host controller, the one reading is Memory mapped mode.
• One host controller, the one programming in indirect mode
• Both needs Maximum transfer bit "MAXTRAN" set
• IO Manager is configured in multiplexed mode.

Could you please check if the memory mounted in this board support the RWW mode or you can share the STM32U5A9J-DK board revision for checking?

An example of RWW is available in  https://github.com/STMicroelectronics/STM32CubeH7RS/tree/main/Projects/STM32H7S78-DK/Examples/XSPI/XSPI_NOR_ReadWhileWrite_DTR.

Please let me know if your request has been answered?

 

Thanks and best regards,

Kaouthar

[sohm]

Hi @KDJEM.1 ,

 

Thank you for your reply. 

• Needs 2 hosts controllers (OCTOSPI)+ IO manager
• One host controller, the one reading is Memory mapped mode.
• One host controller, the one programming in indirect mode
• Both needs Maximum transfer bit "MAXTRAN" set
• IO Manager is configured in multiplexed mode

I really did not understand these above points as I am new to STM platform. If you can please explain a bit in details regarding the driver structure or any links which explains the octo SPI driver . What you meant by 2 host controller ? do we need 2 STM32U5A9J-DK ? 

 

Let's assume we have a octal flash mounted on STM32U5A9J-DK which supports RWW (read while write). Does the driver from STM for STM32U5A9J-DK support that ? I mean both read and write can happen in Parelle , there is no such restriction that read can happen only after the write is completed or vice versa .

Thank You.

 

[KDJEM.1]

Hello @sohm ,

 

Thank you for updating post and I apologize that my last comment caused any confusion.

To start with OCTOSPI interface and external memory, I advise you to take a look at this application note Getting started with Octo-SPI, Hexadeca-SPI, and XSPI Interface on STM32 MCUs - Application note

I mean by Host controller OCTOSPI interface.

For the read while write mode needs a memory supported the RWW have two bank, two OCTOSPIs interface (OCTOSPI1 and OCTOSPI2), OCTOSPI I/O manager. 

What you meant by "Does the driver from STM for STM32U5A9J-DK support that ?" The HAL drivers??

Thank you.

Kaouthar

 

[sohm]

Hi @KDJEM.1 , Thanks for you reply .

In STM32U5A9J-DK the OCTO SPI IO manager has two OCTOSPIs instances (OCTOSPIs Host controller) OCTOSPI1 and OCTOSPI2 and both of them shares the same IO lines in multiplexed mode . In RWW mode we need to have two octo spi host controller (OCTOSPI1, OCTOSPI2) and both of them can access the HAL driver in parallel to perform read and write on the external flash. I have attached one image here for your reference , please correct me if my understanding is wrong.

Do you have a RWW example for STM32U5A9J-DK which uses OCTO SPI interface , this will be a great help.

 

 

Thank You .

[Tesla DeLorean]

NO

The memory IC will not support concurrent operation, it's single threaded, as is the peripheral. You need to arbitrate ownership with a mutex / semaphore.

NOR FLASH is also very slow at ERASE or WRITE, and optimized for READ. For the Write Page/Erase Sector you must wait for the the memory to complete the operation, ie WIP / BUSY (Write-In-Progress)

Or have ONE thread which interacts with the memory, and queue requests against it..

[sohm]

Hi @KDJEM.1  @Tesla DeLorean ,

 

Thank you for the replies .

@KDJEM.1 , 

What you meant by "Does the driver from STM for STM32U5A9J-DK support that ?" The HAL drivers??

Yes Does the Hal OPSI driver supports parallel read and write ? I mean Can I perform read and write simultaneously or as @Tesla DeLorean said the read and write APIs in the HAL driver are blocked by BUSY and WIP flags unless until the read/write operation are finished .

 

@Tesla DeLorean 

According to you then Can I say the the RWW is not possible to be achieved with STM platform  OSPI driver ? If there such BUSY and WIP flag mechanism we can not perform both read and write operation concurrently ?

 

Thank you

[Tesla DeLorean]

I'm saying that the OCTOSPI peripheral does not have multiple contexts to hold different concurrent conversations with the memory IC, so you must arbitrate ownership of the peripheral so it completes whatever operation and phases it's currently involved in, before the next set of operations can start.

I also don't see anything in the MX25UM51245GXDI00 documentation to indicate it can have multiple contexts/threads of operation of read/write, or any queuing methods.

https://www.macronix.com/Lists/Datasheet/Attachments/8967/MX25UM51245G,%201.8V,%20512Mb,%20v1.5.pdf

There are also not separate read / write channels to the MX25, that would facilitate "at the same time" operation you're suggesting, these things would need to be done in a linear, time separated fashion.

The STM32 might be able to operated two different OCTOSPI peripheral/buses "concurrently" to the extent that they can act autonomously, and process data, whilst contending/arbitrating bus/memory usage with other devices vying for resources.