Why I cannot make the I/O lines endure (correct) logic levels
Having designed successfully uC Embedded industrial designs since late '70s, I am confused why I cannot make ANY STM32xyyy design without the following problem: A few seconds/minutes after applying power, one ore more I/O lines begin to fluctuate at analog levels, and it becomes worse as time lapses. Few hours of rest often helps for some seconds. Funny thing is neighboring I/O pin may start to follow other pins logic levels. To focus problem, I have made pcb's with minimal design - just 4 LEDs blinking from Port PB03-PB06. Same problem! Can anyone HELP ME ?!!!!
