XIP mode in CM4

[ujwal_kumar_N_L]

HI, community 

I'm working on QSPI FLASH in STM32H747I DISCO ,i was able to access XIP mode in M7 .
Currently I'm trying to work on M4 tried XIP mode in CM4 but there isn't cache in M4 ,and i was not able to access XIP mode .Is the cache the issue or something else.
The bus architecture doesn't have direct connection between CM4 and Cache memory .Please let me know what might be the issue .
Board uses :STM32H747I
IDE used :Crossworks
Core used M4 (M7 is the main core )

Thank you and regards,

UJWAL KUMAR

[FBL]

Hello @ujwal_kumar_N_L 

Did you try to disable the cache and see if it is configured in memory mapped mode? Here are some suggestions:

1. Disable CPU cache and Systick interrupt before jumping to the QSPI code execution.
2. Setup the main stack pointer MSP and configure the application to be executed on external memory

QUADSPI anticipates the next access and load in advance the byte at the following address. If the subsequent access is indeed made at a continuous address, the access is completed faster since the value is already prefetched.

[mƎALLEm]

Hello,

There is no relation between cache and QuadSPI XIP mode.

Cache is part of cortex M7. No Cache from CM4 side but ART accelerator:

The line I drawn in purple is the path of CM4 access to QSPI through different stages including ART. So no Cache in the path.

[ujwal_kumar_N_L]

How do i access the ART ??

[mƎALLEm]

Hello,

Add this lines at the start:

 __HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */
 __HAL_ART_CONFIG_BASE_ADDRESS(0x90000000UL); /* Configure the Cortex-M4 ART Base address to the QSPI */
 __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */

Note that the accelerator covers only 1Mbyte from the start address.

 

[Tesla DeLorean]

Perhaps more appropriate to copy into SRAM[1,2,3] from the M7 side so you can execute applets on the M4 side?