Issue with second HRTIM PWM output (HRTIM1_CHC1 always stuck at 50% duty cycle)

[noonmirage]

Hello everyone,

I’m working on the STM32G474RE and trying to generate two independent PWM outputs using the HRTIM peripheral. To get started, I followed this tutorial: wiki.st.com/stm32mcu/wiki/Getting_started_with_HRTIM

For my first PWM output, I used:

• Timer: HRTIM1

• Channel: CHA1

• Compare Unit: CMP1

This one works perfectly , the duty cycle changes correctly when I update the compare value.

 

The problem

When I tried to add a second PWM output, I followed the exact same steps as for the first one, except I used:

• Channel: CHC1

• Compare Unit: still CMP1 (as shown in the tutorial)

However, this second output (HRTIM1_CHC1) is always stuck at 50% duty cycle, no matter what compare value I write. Even if I set the compare value very low or very high, the output waveform stays at 0.5 duty cycle.

 

What I checked

• The GPIO pin for CHC1 is correctly configured in alternate function mode.

• The timer is enabled and running.

• The compare register is being updated (I verified in the debugger).

• The first channel (CHA1) continues to work normally.

• No fault or dead‑time configuration is active.

 

My question

Is there something specific about CHC1 or about using the same compare unit (CMP1) on multiple channels that could cause this behavior? Do I need to use a different compare unit for each channel, or is there an additional configuration step required for CHC1?

Any guidance would be greatly appreciated. Thanks in advance!

 

[Gyessine]

Hello @noonmirage 
Since you used our WIKI
Are you sure that you used the same definition, TIMA_DUTY_CYCLE, for the compare value in the compare unit 1 section of the TIMER C configuration?
For reference, I attached a project that generates two PWM signals using TIM A and TIM C, which can be visualized through the PA8 and PB12 pins by changing the duty cycles through the TIMA_DUTY_CYCLE definition in main.h.
You can create a new definition named TIMC_DUTY_CYCLE and modify the TIM C generation code to have two different duty cycles for timer A and timer C.

[Saket_Om]

Hello @noonmirage 

Please make sur that the feature half mode is disabled. 

This mode aims at generating square signal with fixed 50% duty cycle and variable
frequency. It allows to have the duty cycle automatically forced to half of the period value when a new period is programmed.