Question
STM32N6 XIP: HPDMA1 Data Transfer Error - ADC1 with TIM2 Trigger to AXISRAM2
Hi,
Observed Problem
HAL_ADC_Start_DMA() returns HAL_OK, TIM2 starts, ADC begins converting (confirmed via ADC_ISR in debugger), but HPDMA1 Channel 0 immediately raises a DTE (Data Transfer Error), triggering the error callback.
Environment
- MCU: STM32N657X0HXQ
- Boot mode: Two-stage boot — FSBL + XIP Application (external flash via XSPI2, mapped at 0x70100400)
- Toolchain: STM32CubeIDE / GCC
- HAL: STM32CubeN6 (latest)
- Security mode: Full Secure — all code runs in Secure Privileged mode, no NonSecure world
Project Description
This is a minimal reproduction project containing only:
- ADC1 — single channel (PA8 / INP5), triggered by TIM2 TRGO, DMA circular mode
- HPDMA1 Channel 0 — linked-list circular mode, PERIPH_TO_MEMORY, ADC1 → AXISRAM2
- TIM2 — provides ADC trigger at fixed rate (Period=799, no prescaler)
No ETH, no LwIP, no NPU — deliberately stripped down to isolate the DMA issue.
Memory Layout (Linker Script)
ROM (XIP) : 0x70100400, 511K — code in external flashRAM (FLEXRAM) : 0x34000000, 400K — data/bss/heap/stackAXISRAM2_NC : 0x34100000, 64K — DMA node/list/buffer (non-cacheable, NOLOAD)AXISRAM2_C : 0x34110000, 960K — (unused in this project)
DMA Configuration (stm32n6xx_hal_msp.c — HAL_ADC_MspInit)
I Attached all project files, what's the sollution of this issue?c/* 1. Build node */ NodeConfig.NodeType = DMA_HPDMA_LINEAR_NODE; NodeConfig.Init.Request = HPDMA1_REQUEST_ADC1; NodeConfig.Init.Direction = DMA_PERIPH_TO_MEMORY; NodeConfig.Init.SrcInc = DMA_SINC_FIXED; NodeConfig.Init.DestInc = DMA_DINC_INCREMENTED; NodeConfig.Init.SrcDataWidth = DMA_SRC_DATAWIDTH_HALFWORD; NodeConfig.Init.DestDataWidth = DMA_DEST_DATAWIDTH_HALFWORD; NodeConfig.Init.SrcBurstLength = 1; NodeConfig.Init.DestBurstLength = 1; NodeConfig.Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0 | DMA_DEST_ALLOCATED_PORT1; NodeConfig.Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER; NodeConfig.Init.Mode = DMA_NORMAL; NodeConfig.TriggerConfig.TriggerPolarity = DMA_TRIG_POLARITY_MASKED; NodeConfig.SrcSecure = DMA_CHANNEL_SRC_SEC; NodeConfig.DestSecure = DMA_CHANNEL_DEST_SEC; HAL_DMAEx_List_BuildNode(&NodeConfig, &Node_HPDMA1_Channel0); HAL_DMAEx_List_InsertNode(&List_HPDMA1_Channel0, NULL, &Node_HPDMA1_Channel0); HAL_DMAEx_List_SetCircularMode(&List_HPDMA1_Channel0); /* 2. Init handle */ handle_HPDMA1_Channel0.Instance = HPDMA1_Channel0; handle_HPDMA1_Channel0.InitLinkedList.Priority = DMA_LOW_PRIORITY_HIGH_WEIGHT; handle_HPDMA1_Channel0.InitLinkedList.LinkStepMode = DMA_LSM_FULL_EXECUTION; handle_HPDMA1_Channel0.InitLinkedList.LinkAllocatedPort = DMA_LINK_ALLOCATED_PORT1; handle_HPDMA1_Channel0.InitLinkedList.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER; handle_HPDMA1_Channel0.InitLinkedList.LinkedListMode = DMA_LINKEDLIST_CIRCULAR; HAL_DMAEx_List_Init(&handle_HPDMA1_Channel0); HAL_DMAEx_List_LinkQ(&handle_HPDMA1_Channel0, &List_HPDMA1_Channel0); __HAL_LINKDMA(&hadc1, DMA_Handle, handle_HPDMA1_Channel0); /* 3. CID isolation — set after Init */ IsolationConfiginput.CidFiltering = DMA_ISOLATION_ON; IsolationConfiginput.StaticCid = DMA_CHANNEL_STATIC_CID_1; HAL_DMA_SetIsolationAttributes(&handle_HPDMA1_Channel0, &IsolationConfiginput);
Security Configuration (SystemIsolation_Config — called after all peripheral inits)
c__HAL_RCC_RIFSC_CLK_ENABLE(); /* RIMC — ETH1 (not used in this project, kept for completeness) */ RIMC_master.MasterCID = RIF_CID_1; RIMC_master.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_NPRIV; HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_ETH1, &RIMC_master); /* RIFSC — ADC12 */ HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_ADC12, RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_NPRIV); /* HPDMA1 channel security */ HAL_DMA_ConfigChannelAttributes(&handle_HPDMA1_Channel0, DMA_CHANNEL_SEC | DMA_CHANNEL_PRIV | DMA_CHANNEL_SRC_SEC | DMA_CHANNEL_DEST_SEC); /* No RISAF configuration — see problem description */
MPU Configuration
c/* Attribute 0: Write-Back Non-Transient RW-Allocate (cacheable) */ /* Attribute 1: Non-Cacheable */ /* Region 0: FLEXRAM 0x34000000–0x3404FFFF Attr0 RW XN */ /* Region 1: AXISRAM2_NC 0x34100000–0x3410FFFF Attr1 RW XN Outer-Shareable */ /* Region 2: DTCM 0x20000000–0x2001FFFF Attr0 RW XN */ /* Region 3: External Flash 0x70000000–0x73FFFFFF Attr0 RO X */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);