Use __attribute__((interrupt)) for exception handler with GCC on STM32H7

[Gpeti]

Hello,

I am wondering why the STmicro example code (STM32CubeH7) does not use the interrupt attribute for defining exception handlers.

The difference I have noted  when using this attribute is that it forces the stack alignement to 8 bytes:

Example:

 

void f(void);

void handler(void) 
{
 return f();
}

 

 

compiles with arm-none-eabi-gcc 10.2.1 and -O1 -mthumb -mcpu=cortex-m7 in:

 

 

handler():
 push {r3, lr}
 bl f()
 pop {r3, pc}

 

whereas if I add the attribute "interrupt":

 

handler():
 mov r0, sp
 bic r1, r0, #7
 mov sp, r1
 push {r0, lr}
 bl f()
 pop {r0, lr}
 mov sp, r0
 bx lr

 

One can see the difference is in the 3 first instructions that align the stack to 8 bytes. Indeed the stack is not always aligned to 8 bytes inside a function.  From the Procedure Call Standard:

 

6.2.1.1 Universal stack constraints

At all times the following basic constraints must hold:

 Stack-limit ≤ SP ≤ stack-base. The stack pointer must lie within the extent of the stack.
 SP mod 4 = 0. The stack must at all times be aligned to a word boundary.
 A process may only store data in the closed interval of the entire stack delimited by [SP, stack base - 1] (where SP is the value of register r13).

Note

This implies that instructions of the following form can fail to satisfy the stack discipline constraints, even when reg points within the extent of the stack.

ldmxx reg, {..., sp, ...} // reg != sp

If execution of the instruction is interrupted after sp has been loaded, the stack extent will not be restored, so restarting the instruction might violate the third constraint.
6.2.1.2 Stack constraints at a public interface

The stack must also conform to the following constraint at a public interface:

 SP mod 8 = 0. The stack must be double-word aligned.

 

So my questions are:

 

1) why the interrupt attribute is not used in STMicro code ?

2) is there a functional impact to this potentiel bad alignment ?

[Andrew Neil]

I though it was one of the key design features of Cortex-M that it does not require any special attributes for interrupt handlers - they are just plain C functions ?

Do you see other manufacturers doing this ?

 

PS:

See also: Usage of __attribute((interrupt)) of arm-none-eabi-gcc for exception handlers

And: https://stackoverflow.com/a/70657952

[waclawek.jan]

Cortex-M3/4/7 provide automatic 8-byte stack alignment in hardware upon interrupt, see SCB_CCR.STKALIGN bit, which is by default set (and also see the stacked xPSR's bit 9).

In other words, in the normal setting there's no need for the extended prologue/epilogue providing the alignment in software.

JW 

[Gpeti]

I misunderstood the meaning of this bit STKALIGN, thank you for clarifying.

[gbm]

Simple explanation: the code must have been originally written for STM32F1 series which, (only if not fixed with a proper startup code), exhibits a little problem present in the very first version of Cortex-M3 core. The problem is not present in any other Cortex-M core.

[waclawek.jan]

@gbm

> problem present in the very first version of Cortex-M3 core

Can you please elaborate?

Thanks,

JW

[Radosław]

STM32F1  are based on  earlier edytion of core where STKALIGN=0  by default, 

 

[Pavel A.]

Even if the startup aligns the stack on 8 bytes, interrupt can occur after any 4-byte push instruction. So the automatic stack alignment is very helpful.  Cortex-M0 cannot do automatic stack alignment, but it does not have the demanding data types & instructions as well.

So why attribute(interrupt) exists in the ARM Cortex compiler? Maybe it was intended for other non-compliant chips. Or a tiny bug of the compiler: maybe it should ignore this attribute for -mcpu=cortex-m7 , but no one cared to test this.

[Andrew Neil]

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@Pavel A. wrote:

So why attribute(interrupt) exists in the ARM Cortex compiler? 

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Maybe its just a remnant from pre-Cortex days?

Much like the register qualifier in C?