Solved
Bidirectional Communication Between CM4 and CM7 on STM32H747I-DISCO
Working on bidirectional communication between CM4 and CM7 on the STM32H747I-DISCO using FreeRTOS stream buffers (CoreMessageBuffer). One-way communication works fine (either CM4 → CM7 or CM7 → CM4), but both directions at the same time do not work as expected.
What Works:
CM4 → CM7: Data is sent and received correctly.
CM7 → CM4: Works fine when used independently.
Current Issue:
When both directions are enabled simultaneously, it fails to receive data in both the direction.
Memory Section Mapping:
Configured dedicated sections for each direction in both CM4 and CM7 linker files:
.ld
/* CM4 → CM7 */ .xCoreMessageBuffer_section_CM4_to_CM7 : { *(.xCoreMessageBuffer_section_CM4_to_CM7) } > RAM_D3_Z1 .xStreamBufferStruct_section_CM4_to_CM7 : { *(.xStreamBufferStruct_section_CM4_to_CM7) } > RAM_D3_Z2 .ucStorageBuffer_section_CM4_to_CM7 : { *(.ucStorageBuffer_section_CM4_to_CM7) } > RAM_D3_Z3 /* CM7 → CM4 */ .xCoreMessageBuffer_section_CM7_to_CM4 : { *(.xCoreMessageBuffer_section_CM7_to_CM4) } > RAM_D3_Z4 .xStreamBufferStruct_section_CM7_to_CM4 : { *(.xStreamBufferStruct_section_CM7_to_CM4) } > RAM_D3_Z5 .ucStorageBuffer_section_CM7_to_CM4 : { *(.ucStorageBuffer_section_CM7_to_CM4) } > RAM_D3_Z6
These sections are defined in both CM4 and CM7 projects for shared memory access.
What is the issue? If any example code is there for the same can you please provide it!