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Srinath_03
Graduate
December 9, 2025
Question

Cache usage when DMA is used in STM32H745

  • December 9, 2025
  • 2 replies
  • 97 views

Post edited by ST moderator to be inline with the community rules for the code sharing. In next time please use </> button to paste your code and a linker script content. Please read this post: How to insert source code.

Hi im using STM32H745 MCU, in this for cache coherency for using DMA with any peripherals and using Clean and Invalidate data cache Functions will solve the full problem.

if suppose if both the cache and MPU settings are disabled during this time also cache coherency will occur?

MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x00;
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.SubRegionDisable = 0x87;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;

 

this MPU settings is taken from STM32 h7 examples of SPI with DMA normal mode, here some settings are done on MPU, is this will work for all the channels for the DMA. 

since I'm using DMA1 and DMA2 all the channels, this setting is applicable for my use also?.

and one more doubt is if suppose I'm using the DMA circular mode with DMA interrupt disabled, during this time the DMA will running in backside, but I won't be able to see the callback, because interrupt is disabled, so for like this situation also cache coherency will occur or not. the new data will accumulate in the DMA buffer, or it will give the previous buffer data only every time.

 

regards,

Srinath 

    This topic has been closed for replies.

    2 replies

    S
    Saket_Om
    Technical Moderator
    December 9, 2025
    @Srinath_03 wrote:

    if suppose if both the cache and MPU settings are disabled during this time also cache coherency will occur?

    If both the data cache and MPU are disabled, then cache coherency issues do not occur because:

    • The CPU accesses memory directly (no cache in between).
    • DMA also accesses memory directly.
    @Srinath_03 wrote:

    this MPU settings is taken from STM32 h7 examples of SPI with DMA normal mode, here some settings are done on MPU, is this will work for all the channels for the DMA. 

    since I'm using DMA1 and DMA2 all the channels, this setting is applicable for my use also?.

    The MPU settings are not per DMA channel, but per memory region. If your DMA buffers are all in the same region, one MPU setting can cover them. If they are in different regions, you need to configure each region accordingly.

    M
    mƎALLEm
    Technical Moderator
    December 9, 2025

    Hello,

    This (default/background MPU) configuration:

    MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = 0x00;
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.SubRegionDisable = 0x87;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;

    is mandatory to prevent CM7 speculative access to invalid memory regions especially for the non-configured external memories. Nothing to do with the cache coherency. 

    Please refer to this thread for its explanation.

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