Clarification on DMA arbitration: is memory-to-memory different?

[PhucXDoan]

I'm not much of an avid reader, but does this say what I think it says?

When a channel x is programmed for a block transfer in memory-to-memory mode, rearbitration is considered between each single DMA transfer of this channel x. Whenever there is another concurrent active requested channel, the DMA arbiter automatically alternates and grants the other highest-priority requested channel, which may be of lower priority than the memory-to-memory channel.

 

Does this mean that if I have a memory-to-memory DMA channel and a memory-to-peripheral DMA channel, the DMA arbiter will ping-pong back and forth between the two channel's transfers if their requests are activate at the same time? Even if the memory-to-memory channel is of higher priority than the memory-to-peripheral channel? Or am I misreading this?

If I am right, why treat memory-to-memory specially?

[waclawek.jan]

> Even if the memory-to-memory channel is of higher priority than the memory-to-peripheral channel?

Yes, that's what the quoted text says.

> If I am right, why treat memory-to-memory specially?

I am not ST, but presumably M2P/P2M transfers are more important than M2M, and also sparse enough to allow reasonable M2M transfers bandwidth even if the latter suffers the penalty imposed by the above mechanism.

Although I realize, that that's not a good argument, as the user might always set the priorities so that M2P/P2M transfers are preferred to M2M transfers. Not all ST decisions are strictly rational.

JW