Clock source for OTG_HS and its USB_OTG_EMBEDDED_PHY

[Emelm.1]

Which clock is used for clocking the OTG_HS and its USB_OTG_EMBEDDED_PHY while in FS mode? Is it Fvco / PLLQ?

stm32f4

[waclawek.jan]

It's not very clear from the RM, but most of the OTG modules runs probably out of the AHB clock, with only a synchronizer/interface portion running at the PHY clock, which comes, as you've said, from Q output of PLL (aka 48MHz clock).

Don't enable the ULPI clock in RCC. Note, that it's enabled by default in the LP version of enable registers.

JW

[TDK]

In external PHY mode, PLLQ isn't needed at all, so unlikely that the peripheral is using this clock.