Clocksource for USB-Host (STM32H7)

[PBull]

Hello,

I'm developing a USB-Host application (MSC / Fullspeed) with the STM32H743 µC (using STM32H743I-EVAL2 Board)

The application works fine when using PLL3Q as clocksource.

But when I use PLL1Q or RC48 as clocksource the USB "Core soft reset" timed out:

OTG->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; // Core soft reset
 
// Wait Core reset to finish, max 100 ms
tout_ms = 100U;
while ((OTG->GRSTCTL & USB_OTG_GRSTCTL_CSRST) != 0U) {
 if (tout_ms == 0U) {
 return ARM_DRIVER_ERROR_TIMEOUT;
 }
 tout_ms--;
 HAL_Delay(1U);
}
HAL_Delay(1U);

I mapped RC48 to MCO1 to check if there is an 48MHz output and it is.

I checked the RCC/USB registers but couldn't find anything suspicious.

Does anyone has an idea what's wrong here?

Thanks,

Peter

[berendi]

Can you post the contents of all RCC registers for the working and non-working cases?

[PBull]

Hi,

sure, here is a picture, mapping all changed RCC registers just before the soft reset should occur.

On the left the working PLL3 configuration and on the right the non working RC48 configuration.

[berendi]

HSI48 should be calibrated to some external source with the CRS peipheral, either to LSE or a SOF signal coming from another host. CRS is not running (APB1HENR = 0), LSE is not running (BDCR = 0), and there is no incoming SOF because you are the host.

This should not prevent an USB core reset though, but I am not exactly sure what an unconfigured CRS would do to HSI48. Anyway, not a healthy configuration.

[waclawek.jan]

And what if you remove the timeout, does the reset hang forever?

JW