Core Coupled Memory (CCM) for Class B Certification

[rokamura]

Hi, my company is pursuing a UL1998 (very similar to IEC 60730-1) Functional Safety Certification.  In reading the ST Application Note (AN4435) I see in section 3.3 SRAM Tests, it says "Some ST Microcontrollers feature a built-in word protection with single-bit redundancy (hardware parity check) applied on CCM RAM or at least on a part of the SRAM." 

On our current project, we are using an STM32F429ZI MCU and I see it has 64kB of CCM, but am having trouble finding documentation for its use.   In a handful of forums, I have seen them discuss how CCM is only accessible by the CPU (rather than also by DMA), but I cannot find anywhere else alluding to it having a built-in hardware parity check.  I wanted to see if someone could point me to documentation on this or at least confirm that the CCM in the STM32F429ZI does have the hardware parity check, and if so, what happens if the hardware parity check fails on startup or during runtime.  

[Petr Sladecek]

Hello,

Table 7 at AN4435 (as well as safety related presentation available on ww.st.com) gives an overview which STM32 products feature parity bit or ECC protection on RAM. The STM32F4 family is not the case. If such a protection is available, it should be described at product Reference manual.

Best regards,

Petr

[Tesla DeLorean]

I don't recall the F429 having this.

Typically parts that do fail with an NMI, and you're expected to clear the RAM before enabling usage so there aren't undefined cells. Similarly FLASH Line words with ECC need to be fully written post erasure.

Can you CRC and check your structures to achieve similar or better levels of detection and recovery?

[Petr Sladecek]

The matter is to prevent any parity/ECC error when an unexpected reading appears from a 'virgin' location which was not written previously. The residual protection bits are accidental and not set at this case.

Best regards,

Petr