Cortex-M3 NVIC config with FreeRTOS

[RLepa.1]

I'm working on a legacy projected using FreeRTOS v7.3.0 on an STM32F205 Cortex-M3.

My system intermittently lands in the hard fault exception handler, and/or watchdog resets.

I have tracked down some issues with the NVIC config:

1. Using NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1) instead of NVIC_PriorityGroup_4. NVIC_PriorityGroupConfig() is from STM StdPeriph Driver Lib v1.1.0.
2. Not all app isr priorities below configMAX_SYSCALL_INTERRUPT_PRIORITY. Some of the isrs are big, so rather than verifying no FreeRTOS API calls, I made sure all app isr priorities are a lower priority (higher priority number) than the current configMAX_SYSCALL_INTERRUPT_PRIORITY setting of 5.

These fixes in test, but being an intermittent problem, are there any other NVIC/interrupt related gotchas with FreeRTOS/Cortex-M3 that I should be aware of?

Thanks,

-Rob

[Pavel A.]

> Some of the isrs are big, so rather than verifying no FreeRTOS API calls, I made sure all app isr priorities are a lower priority (higher priority number) than the current configMAX_SYSCALL_INTERRUPT_PRIORITY setting of 5.

If these "big ISRs" really make FreeRTOS calls, it is not enough to move them to priority lower than configMAX_SYSCALL_INTERRUPT_PRIORITY. Special variants of FreeRTOS APIs must be used from interrupt handlers.

Using NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1) could be OK. You get two levels. But then configMAX_SYSCALL_INTERRUPT_PRIORITY must be set to allowed level (5 is not).