DMA to GPIO control using timer is not working

[Soad]

I want to control GPIO output using DMA and Timer. The target is generating a CLK signal of 1MHz and control PB0 synchronized with the CLK.

I am using Nucleo-F411RE as the development board. I have followed the instructions from the forum and configured the program.

Configuration:

HCLK: 100MHz

Timer3:

 

 Program in main.c:

 

uint32_t dummy_data[7] = {0} ;
dummy_data[0] = 0x00000001 ;
dummy_data[1] = 0x00010000 ;
dummy_data[2] = 0x00000000 ;
dummy_data[3] = 0x00000000 ;
dummy_data[4] = 0x00000001 ;
dummy_data[5] = 0x00010000 ;
dummy_data[6] = 0x00000000 ;

HAL_DMA_Start(&hdma_tim3_ch4_up, (uint32_t)dummy_data, (uint32_t)&(GPIOB->BSRR), 7) ;
HAL_TIM_Base_Start(&htim3) ;
HAL_TIM_OC_Start(&htim3, TIM_CHANNEL_4) ;
TIM3->DIER |= (1 << 8 )  ;

 

I am expecting to see a pulse in PB0 synchronized with PC9 PWM. 

But as output, I am getting only 1MHz PWM in PC9 and there is no change in PB0.

Am I missing something? Any suggestions would be helpful.

 

[Tesla DeLorean]

You need to use DMA2 for the memory to memory mode, and a TIM on APB2 to trigger the process.

[Soad]

• Why memory to memory mode? Why not memory to peripheral? As far I understand memory to peripheral mode is used to write to peripheral registers.
• Why DMA2 why not DMA1 on APB1 timer ? 

[Soad]

• Why memory to memory mode? Why not memory to peripheral? 
• Why DMA2 why not DMA1 on APB1 timer ? 

[Tesla DeLorean]

Why's it not working?

Which bus is the GPIOB on exactly?

Only DMA2 of the F2/F4 supports M2M operation. DMA2 is bonded to APB2 and the TIM on it. DMA1 to APB1, but doesn't support the two step M2M requires.

[Soad]

Thank you for your suggestion. I have configured the TIM1 PWM CN1 to trigger the DMA and used DMA2 Stream 5 in Memory to peripheral mode to write words in GPIOB->BSRR. Now it works (Can write the GPIOB->BSRR register successfully).

 

[waclawek.jan]

> Why memory to memory mode? Why not memory to peripheral? As far I understand memory to peripheral mode is used to write to peripheral registers.

While in DMA control register you correctly set memory-to-peripheral mode, the data are not transferred to an APB peripheral, as GPIO is not on APB but on AHB, so from the busmatrix point of view the transfer goes from memory (on AHB) to another memory-like position (on another AHB). And in 'F4 there's no connectivity from the Peripheral port of DMA1 onto the AHBs, that's why only DMA2 can be used.

JW

[Soad]

@waclawek.jan  Thank you very much. You have just cleared up my confusion.