Ethernet is not working when using STM32H7 with KSZ8x95

[mayank]

Hello @Imen.D,

We still have this issue on certain custom boards designed in-house. We use KSZ8095 on some and KSZ8895 (5 port) on others with same base circuit over MII/MDIO. 

We have tested the clock signals and they seemed to meet the STM32H7 signal requirements per the datasheet . However we also tested that some clock rates greater than 2.5MHz didn't work more frequently than 2.5MHz.

 

Also we follow the link you shared for initializing. What else can we look at?

 

Thanks,

Mayank.

[Imen.D]

Hello @mayank ,

I create for you a new thread instead of posting in the old one (which is already solved).

This will increase the chances of getting you a reply from our community members and our experts.

@STea

[STea]

Hello @mayank ,

To be able to help you with your issue we need to know more about your design and process as well as your Firmware it will be great if you can share with us your schematics and you code or the steps you used to configure the Ethernet as well as you Network interface.

after a quick look in the documentation of the KSZ8895 a general recommendation is to make sure that you are respecting the Reset circuit recommendation from the manufacturer (see KSZ8895MQX/RQX/FQX/MLX Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface (microchip.com) section 8. Reset Circuit)

BR

 

[mayank]

Hello BR,

We have followed the circuit as described in KSZ8895 and KSZ8081 phys.

We use Nuttx and drivers provided by Nuttx to setup Ethernet. We have confirmed that the sequence of initializing Phy and MAC is exactly the same as HAL code generated by CubeMX. 

Our EE also noted that SWR bit is more likely to be rest by the CPU if RX and TX clks are 2.5MHZ (10mbps) however I think that's anecdotal.

Below is the example of KSZ8081 based schematic. I have also attached stm32_ethernet.c. Relevant functions are 

stm32_phyinit() which resets the KSZ8081 phy and sets up auto-negotiate or speed. It is called by stm32_ethconfig which also calls stm32_ethreset where SWR bit is set and waits for it to be cleared.

Here is the rest of the schematic for KSZ8081

 

 

[STea]

Hello @mayank ,

I have tried to simulate the reset circuit i don't know the reason behind adding the D29 diode and from my side I see that this diode is preventing the PHY from resetting Hince not being able to asset the SWR reset in MAC side.

can you please probe the output of the reset circuit and confirm this, maybe try to remove or bypass this diode and see if that changes behavior on the reset going to the PHY.
here is what I see:

 

BR  

[mayank]

Hello BR,

My EE confirmed that the ethernet chip IS coming out of the reset. He also confirmed that he didn't find any use of D29 as well and removed it for the testing.

Any thing else we can check?

 

[STea]

Hello @mayank ,

can you please check if the RX and TX clk going to the MCU with the scope and make sure it is clocking correctlly .
coming back on you statement "Our EE also noted that SWR bit is more likely to be rest by the CPU if RX and TX clks are 2.5MHZ (10mbps) however I think that's anecdotal."  can you please elaborate more on this ?
also a good test to eliminate the Software component potential issue from our investigation is to test you code using  Nuttx on one of our nucleo or disco boards because we don't support this in our Cube Firmware package.

Regards