External SPI Flash Clock not being set for M4, Zephyr driver

[Simon33rd]

Hi All,

I've had the external SPI Flash driver working on the STM32H745_M7, using Zephyr SDK 4.0.0.

But when I setup it up on the M4 side the driver initialization is failing with error:

[1;31m<err> spi_ll_stm32: Could not select SPI domain clock

Further investigation shows that stm32_clock_control_configure(), is called from spi_stm32_init(), and fails to setup the clock path.  In particular it is seeing that PLL_Q clock is not enabled.  PLL 1 is setup on the M7 side and it doesn't look like I should be enabling it again in the M4's device tree again.

How do I get the correct clock path setup for the SPI driver on the M4 side? I need to run the external SPI flash from the M4.

 

Thanks,

Simon

[Sarra.S]

Hello @Simon33rd, Could you share the dts for the M4 side?

[Simon33rd]

Hi Sarra,

Have you been able to look at this for me?

[Simon33rd]

Hi Sarra,

My board .dts settings and the resulting build zephyr.dts attached.

I did also try and use PLL3 given that PLL1 is setup on the M7 side, but I still get the same error.

by the way what is  < &rcc 0x9 0xec50 > doing? I can see the first part is enabling SPI123 clock.

 

 

clocks = < &rcc 0xf0 0x1000 >, < &rcc 0x9 0xec50 >;

 

[Simon33rd]

Hi All,

I managed to find a workaround to the problem I was having.  On the M7 side I was able to get SPI1 to use either the PLL1_Q clock or the PLL3_P clock.  I wanted to use the PLL3_P clock to maximize the SPI clock to 50MHz, as it's 48MHz when using PLL1_Q (because I'm running at 480MHz and the highest DIVQ1 can be is /5).

On the M4 side I setup the PLL3 in the device tree (for the M4 Zephyr OS) and select this clock in &spi1:

 

 

clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
	 <&rcc STM32_SRC_PLL3_P SPI123_SEL(2)>;​

 

This doesn't and I get this runtime error:

 

[00:00:00.200,000] <err> spi_ll_stm32: Timeout waiting for transfer complete
[00:00:00.200,000] <err> spi_nor: Failed to wait until flash is ready (-116)
*** Booting Zephyr OS build v4.0.0 ***
is25le01g@0: device not ready.
 

 

It looks like the SPI123 clock is not being setup.  After some trial and error. I found that enabling the PLL3 (on the M4 side) but selecting the PLL1_Q clock on the clock Mux worked (SPI123_SEL(0)), and I get the 48MHZ SPI_CLK.

My device tree setup is as follows:

 

&clk_hse {
	clock-frequency = <DT_FREQ_M(32)>; 
	status = "okay";
};

&pll3 {
	div-m = <2>;
	mul-n = <50>;
	div-p = <4>;
	div-q = <4>;
	div-r = <4>;
	clocks = <&clk_hse>;
	status = "okay";
};

// External SPI NOR flash
&spi1{
 status = "okay";
	pinctrl-0 = < &spi1_nss_pg10 &spi1_sck_pg11
		 &spi1_miso_pg9 &spi1_mosi_pb5>;
	pinctrl-names = "default";
	clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
			 <&rcc STM32_SRC_PLL3_P SPI123_SEL(0)>;
	// cs-gpios must be disabled to use hardware SS
	//cs-gpios = <&gpiog 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
	fifo-enable;
	spi_nor_1g: is25le01g@0 {
 compatible = "jedec,spi-nor";
		reg = < 0x0 >;
 status = "okay";
		// 50MHz max frequency for standard SPI
 spi-max-frequency = < 50000000 >;
 jedec-id = [ 9D 60 1B ];
 size = < 0x40000000 >;
		//spi-cpol; /* Clock Polarity: 1 = idle high */
 //spi-cpha; /* Clock Phase: 1 = sample on rising edge */
		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;
			storage_partition: partition@00000 {
				label = "storage";
				reg = <0x00000000 DT_SIZE_M(132)>;
			};
		};
 };
};

 

Not ideal but it's working.

Simon