FileX, DMA, disable or manage cache?

[OHaza.1]

Hi

In the various filex with SDMMC examples the icache and dcache are enabled so when porting I did the same.

I noticed when attempting to use DMA SPI it was not working until I disabled these.

For the SD I then have to disable cache and cache management and as far as I can tell it works, if not then then the attempts to invalidate and clean the cache result in hardfault.

Is this a reasonable solution? Or should the cache be enabled and managed by invalidating the cache for the DMA SPI reads?

Thanks in advance

[Tesla DeLorean]

Disabling caches degrades performance of everything.

Best to manage specific buffers, with suitable alignment, limited scope and avoid collateral damage to surrounding data/structures.

[OHaza.1]

Thanks.

So, declare buffers with ALIGN_32BYTES

Before each DMA SPI operation, the address TX buffer should be cleaned and RX invalidated.

I have no idea what the performance hit of this invalidation is, perhaps for small ~4 byte operations it's simpler to poll.

[Haithem Rahmani]

Hi,

Another solution is to allocate the buffers in an uncached area by configuring the MPU, without the need to disavble the cache.

regards

Haithem.

[Piranha]

https://community.st.com/s/question/0D53W00001Z9K9TSAV/maintaining-cpu-data-cache-coherence-for-dma-buffers

> for small ~4 byte operations

Put the buffers in a memory configured as non-cacheable by MPU.

[OHaza.1]

thanks, I will have to look at the MPU examples to understand how this is done.

Invalidating the cache before seemed to be sufficient, although from the above example it appears as though it needs to be done after as well..

In my specific case, depending on the size of the message being read in it could be more or less than 32 bytes, although as mentioned the spi commands are usually around 4 bytes.