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TGrun.534
Visitor II
February 21, 2020
Question

found a wrong definition in library from cube for STM32f4xx

  • February 21, 2020
  • 1 reply
  • 578 views

I think on definition of Limit 3 is a error in the firmwarelibrary

Both OR are the same values.

#define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000U 
#define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) 
#define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) 
#define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) 
#define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) 
#define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) 
#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0)

Datasheet says

Bits 15:14 DMA: Direct memory access mode for multi ADC mode

This bit-field is set and cleared by software. Refer to the DMA controller section for more

details.

00: DMA mode disabled

01: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)

10: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)

11: DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2)

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    1 reply

    I
    Imen.D
    Technical Moderator
    February 26, 2020

    Hello,

    You are right, I confirm this issue and we will fix it and verify if there is other impacted series.

    In fact, the define in the stm32f4xx_ll_adc.h for "LL_ADC_MULTI_REG_DMA_LIMIT_3" and "LL_ADC_MULTI_REG_DMA_UNLMT_3" should be:

    #define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_1 | ADC_CCR_DMA_0) 
#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_1 | ADC_CCR_DMA_0)

    instead of:

    #define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0)
#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0)

    Thank you for your contribution and highlighting this.

    Best Regards,

    Imen

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