How is CMSIS DSP and NN library implement using SIMD instruction and FPU?

[SSRIN.1]

I came across a documentation stating that arm m4+ processors have CMSIS DSP api that is implemented with SIMD instructions. When we try to take the library file to use it there are 2 variants single precision and doubles precision FPU. I assumed that FPU is a hardware unit with its own instructions to accelerate calculations , however after reading about SIMD I am confused how SIMD and FPU are related to CMSIS DSP library.

[Andrew Neil]

Please give a link to that document for context.

Googling "Cortex-M4 SIMD" gives this whitepaper:

https://community.arm.com/cfs-file/__key/communityserver-blogs-components-weblogfiles/00-00-00-21-42/7563.ARM-white-paper-_2D00_-DSP-capabilities-of-Cortex_2D00_M4-and-Cortex_2D00_M7.pdf

Perhaps that helps you?

It's not really anything specifically to do with STM32