How to configure STM32F4 Ethernet DMA vs. general-purpose DMA priority?

[Szabi]

Hi,

I have an application where general-purpose DMA (triggered by TIM peripheral) timing is critical. I found that when there's communication over Ethernet, the timing requirements for the GP DMA are occasionally not met. I'm thinking that this might be an arbitration/priority issue between the Ethernet DMA and the GP DMA. Is this possible? Can an Ethernet DMA transfer block GP DMA transfers? If yes, how do I give priority to the GP DMA over the Ethernet DMA? I'd appreciate any pointers.

Thanks, Szabi

[waclawek.jan]

Which 'F4?

> Can an Ethernet DMA transfer block GP DMA transfers?

Yes, to certain extent, if it uses bursts. See ETH_DMABMR and Host bus burst access subchapter of ETH chapter in RM.

Other than that, it's one of the masters on the busmatrix, which is said to be round-robin arbitrated, so if ETH and CPU and the second DMA attempts to access the same memory in the same moment than your "critical" DMA, it will be delayed by 3 AHB cycles (assuming you have no LTDC and HS_USB with enabled DMA).

A simple way to avoid collision with ETH is to use a different SRAM. You have at least two probably in every 'F4 which has ETH.

JW