How to make Ethernet and lwIP working on STM32
This is an umbrella topic where I will collect the key problems and solutions to finally get networking on STM32 working. The issues formatted as bold are the most critical ones.
HAL ETH drivers have been significantly reworked since the following firmware packages: CubeF4 v1.27.0, CubeF7 v1.17.0, CubeH5 v1.0.0, CubeH7 v1.10.0
Series: F1, F2, F4, F7, H5, H7 (all STM32 with Ethernet)
- lwIP driver Tx deadlock. [reworked drivers]
- Missing compiler and CPU memory barriers. [legacy drivers]
- RMII mode not enabled because of lacking SYSCFG synchronization. [legacy drivers]
- Unwanted interrupts not masked.
- CubeMX generates wrong PHY configuration. [legacy drivers]
- Not possible to use a custom PHY driver in CubeMX. [reworked drivers]
- Wrong clock source and PLL configuration. [examples]
- lwIP driver zero-copy Rx PBUF pool size is inappropriate. [reworked drivers]
- CubeMX generates broken lwippools.h file for C++.
- CubeMX generates a dysfunctional lwIP application without RTOS.
- Unnecessary delay in LAN8742_Init() and link state management in low_level_init(). [reworked drivers]
- Unnecessary delays and peripheral reset in HAL_ETH_Init() function.
- Multiple flaws in a PTP API implementation. [reworked drivers]
- Poorly chosen MDIO frequency limits and scarce documentation.
Series: F1, F2, F4, F7 (older Synopsys basic peripheral)
- Many flaws as a result from incorrect porting of the reworked H7 series HAL ETH driver. [reworked drivers]
- No DMA access to a data in FLASH memory. [reworked drivers]
- Tx complete interrupt not triggered. [legacy drivers] The related documentation is also wrong.
- Wrong Tx checksum offload documentation.
- Wrong PTP clock source documentation.
- Wrong PPS output documentation.
Series: H5, H7 (newer Synopsys QoS peripheral)
- HAL ETH driver sets wrong MDIO frequency.
- Wrong descriptor ring length documentation.
- Wrong and misleading descriptor tail pointer documentation.
- Wrong or scarce DMA Rx resuming documentation.
Series: F7, H7 (Cortex-M7 CPU)
- Flawed MPU configuration and D-cache maintenance in lwIP driver. [reworked drivers]
- Overlapping and merged memory regions in linker script files.
- Critical spelling errors in linker script files.
- The example code in the article "DMA is not working on STM32H7 devices" is flawed in multiple ways.
lwIP API related:
- Ethernet link and DHCP management code is not thread-safe. When used with RTOS, the code ignores lwIP requirements described in Common pitfalls and Multithreading.
- The example code in the article "How to create project for STM32H7 with Ethernet and LwIP stack working" is not thread-safe. It uses RTOS and lwIP RAW API, but doesn't do lwIP core locking.
- Improper use of NETIF and link up/down statuses. The meaning of netif_set_up()/netif_set_down() functions changed in v2.0.0, but ST's code is not updated. Now NETIF must be up regardless of link state, but for a link state only the functions netif_set_link_up()/netif_set_link_down() must be used.
- Improper use of DHCP client. The code is for an outdated version of DHCP client, which needed external state management. Current versions fully manage the state internally. Monitoring of the state and reporting IP addresses can be done by a callback set up with netif_set_status_callback() without wasting a thread on it.
Other related information:
Another detailed topic by @alister: "[bug fixes] STM32H7 Ethernet". While mostly dedicated to H7 series, it also has a good amount of information relevant to all Ethernet/lwIP related development.
Open source zero-copy Ethernet/lwIP driver example. The hardware driver is for F2 series, which means that it's almost the same for all Fx series. The lwIP related code and general ideas are still valid for all series.
My other closely related topic: "Actually working STM32 Ethernet and lwIP demonstration firmware". As that topic is currently unavailable, because ST still has not moved it to the new forum, I am attaching a PDF copy of that topic and the related firmware files to this topic.